{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,22]],"date-time":"2024-10-22T20:46:42Z","timestamp":1729630002365,"version":"3.28.0"},"reference-count":12,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2014,5]]},"DOI":"10.1109\/icicdt.2014.6838602","type":"proceedings-article","created":{"date-parts":[[2014,7,28]],"date-time":"2014-07-28T15:03:50Z","timestamp":1406559830000},"page":"1-4","source":"Crossref","is-referenced-by-count":1,"title":["Cross logic: A new approach for defect-tolerant circuits"],"prefix":"10.1109","author":[{"given":"Mariem","family":"Slimani","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Arwa","family":"Ben Dhia","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Lirida","family":"Naviner","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/ASMC.2003.1194504"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2006.32"},{"journal-title":"Mentor Graphics Tessent CellModelGen Tool","year":"0","author":"graphics","key":"10"},{"key":"1","first-page":"1247","article-title":"Yield and reliability issues in nanoelectronics technologies","author":"teixeira franco","year":"2006","journal-title":"Annals of Telecommunications December"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1016\/j.microrel.2009.08.001"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2012.2213102"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/DFT.2010.19"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1016\/j.microrel.2013.06.014"},{"key":"9","volume":"17","author":"bushnell","year":"2000","journal-title":"Essentials of Electronic Testing for Digital Memory and Mixed-Signal VLSI Circuits"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/NEWCAS.2010.5603933"},{"key":"11","first-page":"2771","article-title":"Fault-tolerance of robust feed-forward architecture using single-ended and differential deepsubmicron circuits under massive defect density","author":"stanisavljevic","year":"2006","journal-title":"Neural Networks 2006 IJCNN\"06 International Joint Conference On IEEE"},{"key":"12","doi-asserted-by":"crossref","DOI":"10.1109\/DFT.2013.6653592","article-title":"Evaluating CLB designs under multiple SETs in SRAM-based FPGAs","author":"ben dhia","year":"2013","journal-title":"IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS)"}],"event":{"name":"2014 IEEE International Conference on IC Design & Technology (ICICDT)","start":{"date-parts":[[2014,5,28]]},"location":"Austin, TX, USA","end":{"date-parts":[[2014,5,30]]}},"container-title":["2014 IEEE International Conference on IC Design &amp; Technology"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6832295\/6838579\/06838602.pdf?arnumber=6838602","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,8,13]],"date-time":"2019-08-13T04:09:31Z","timestamp":1565669371000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6838602\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,5]]},"references-count":12,"URL":"https:\/\/doi.org\/10.1109\/icicdt.2014.6838602","relation":{},"subject":[],"published":{"date-parts":[[2014,5]]}}}