{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,5]],"date-time":"2024-09-05T17:56:12Z","timestamp":1725558972616},"reference-count":8,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2015,6]]},"DOI":"10.1109\/icicdt.2015.7165911","type":"proceedings-article","created":{"date-parts":[[2015,7,27]],"date-time":"2015-07-27T17:17:27Z","timestamp":1438017447000},"page":"1-4","source":"Crossref","is-referenced-by-count":2,"title":["Impact of local interconnects on ESD design"],"prefix":"10.1109","author":[{"given":"Mirko","family":"Scholz","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Shih-Hung","family":"Chen","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Geert","family":"Hellings","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Dimitri","family":"Linten","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Roman","family":"Boschke","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/IRPS.2013.6531970"},{"journal-title":"International Technology Roadmap for Semiconductors (ITRS)","year":"2013","key":"ref3"},{"journal-title":"DECIMM Angstrom Design Automation","year":"0","key":"ref6"},{"key":"ref5","article-title":"Transmission line pulsing techniques for circuit modeling of ESD Phenomena","author":"maloney","year":"1985","journal-title":"Proceedings EOS\/ESD Symposium"},{"journal-title":"White Paper","article-title":"Industry Council on ESD target levels","year":"2007","key":"ref8"},{"key":"ref7","article-title":"On Gated Diodes for ESD protection in a bulk FinFET CMOS technology","author":"thijs","year":"2011","journal-title":"ESD Symposium Proc"},{"key":"ref2","article-title":"A 22 nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors","author":"auth","year":"2012","journal-title":"Proceedings VLSI Technology"},{"key":"ref1","article-title":"High performance 32nm logic technology featuring 2nd generation high-k + metal gate transistors","author":"packan","year":"2009","journal-title":"IEDM Technical Digest"}],"event":{"name":"2015 International Conference on IC Design & Technology (ICICDT)","start":{"date-parts":[[2015,6,1]]},"location":"Leuven, Belgium","end":{"date-parts":[[2015,6,3]]}},"container-title":["2015 International Conference on IC Design &amp; Technology (ICICDT)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7153312\/7165871\/07165911.pdf?arnumber=7165911","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,25]],"date-time":"2017-03-25T01:34:57Z","timestamp":1490405697000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7165911\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,6]]},"references-count":8,"URL":"https:\/\/doi.org\/10.1109\/icicdt.2015.7165911","relation":{},"subject":[],"published":{"date-parts":[[2015,6]]}}}