{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,6]],"date-time":"2024-10-06T00:56:04Z","timestamp":1728176164588},"reference-count":11,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2018,6]]},"DOI":"10.1109\/icicdt.2018.8399777","type":"proceedings-article","created":{"date-parts":[[2018,7,3]],"date-time":"2018-07-03T01:15:04Z","timestamp":1530580504000},"page":"145-148","source":"Crossref","is-referenced-by-count":10,"title":["Sequential 3D: Key integration challenges and opportunities for advanced semiconductor scaling"],"prefix":"10.1109","author":[{"given":"A.","family":"Vandooren","sequence":"first","affiliation":[]},{"given":"L.","family":"Witters","sequence":"additional","affiliation":[]},{"given":"J.","family":"Franco","sequence":"additional","affiliation":[]},{"given":"A.","family":"Mallik","sequence":"additional","affiliation":[]},{"given":"B.","family":"Parvais","sequence":"additional","affiliation":[]},{"given":"Z.","family":"Wu","sequence":"additional","affiliation":[]},{"given":"A.","family":"Walke","sequence":"additional","affiliation":[]},{"given":"V.","family":"Deshpande","sequence":"additional","affiliation":[]},{"given":"E.","family":"Rosseel","sequence":"additional","affiliation":[]},{"given":"A.","family":"Hikavyy","sequence":"additional","affiliation":[]},{"given":"W.","family":"Li","sequence":"additional","affiliation":[]},{"given":"L.","family":"Peng","sequence":"additional","affiliation":[]},{"given":"N.","family":"Rassoul","sequence":"additional","affiliation":[]},{"given":"G.","family":"Jamieson","sequence":"additional","affiliation":[]},{"given":"F.","family":"Inoue","sequence":"additional","affiliation":[]},{"given":"G.","family":"Verbinnen","sequence":"additional","affiliation":[]},{"given":"K.","family":"Devriendt","sequence":"additional","affiliation":[]},{"given":"L.","family":"Teugels","sequence":"additional","affiliation":[]},{"given":"N.","family":"Heylen","sequence":"additional","affiliation":[]},{"given":"E.","family":"Vecchio","sequence":"additional","affiliation":[]},{"given":"T.","family":"Zheng","sequence":"additional","affiliation":[]},{"given":"N.","family":"Waldron","sequence":"additional","affiliation":[]},{"given":"V.","family":"De Heyn","sequence":"additional","affiliation":[]},{"given":"D.","family":"Mocuta","sequence":"additional","affiliation":[]},{"given":"N.","family":"Collaert","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","article-title":"Permanent wafer bonding in low temperature using plasma enhanced chaemical vapour deposition of various dielectrics","author":"kim","year":"2015","journal-title":"IEEE Intl 3D Systems Integration Conf"},{"key":"ref3","article-title":"Gate Stack Thermal Stability and PBTI Reliability Challenges for 3D Sequential Integration: Demonstration of a suitable gate stack for top and bottom tier nMOS","author":"franco","year":"2016","journal-title":"IRPS"},{"journal-title":"Low-temperature pre-epitaxy surface cleaning for Si and SiGe","year":"2015","author":"proijt","key":"ref10"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/S3S.2016.7804375"},{"key":"ref11","article-title":"The potential of sequential-3D integration for advanced semiconductor scaling","author":"vandooren","year":"2018","journal-title":"Chip-scale review magazine to be published"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.23919\/VLSIT.2017.7998181"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/S3S.2017.8309234"},{"key":"ref7","article-title":"Junctionless gate-alI-around lateral and vertical nanowire FETs with simplified processing for advanced logic and analog\/RF applications and scaled SRAM cells","author":"veloso","year":"2016","journal-title":"VLSI"},{"key":"ref2","article-title":"The impact of Sequential-3D integration on semiconductor scaling roadmap","author":"mallik","year":"2017","journal-title":"IEDM"},{"key":"ref9","article-title":"Highly Doped Low-Temperature Si:P Growth for Source\/Drain Formation in Advanced Si nFETs","author":"rosseel","year":"2017","journal-title":"MRS Conf"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2011.6131506"}],"event":{"name":"2018 International Conference on IC Design & Technology (ICICDT)","start":{"date-parts":[[2018,6,4]]},"location":"Otranto","end":{"date-parts":[[2018,6,6]]}},"container-title":["2018 International Conference on IC Design & Technology (ICICDT)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8391403\/8399713\/08399777.pdf?arnumber=8399777","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2018,7,23]],"date-time":"2018-07-23T22:55:15Z","timestamp":1532386515000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8399777\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,6]]},"references-count":11,"URL":"https:\/\/doi.org\/10.1109\/icicdt.2018.8399777","relation":{},"subject":[],"published":{"date-parts":[[2018,6]]}}}