{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,5]],"date-time":"2024-09-05T10:34:43Z","timestamp":1725532483939},"reference-count":12,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2018,12]]},"DOI":"10.1109\/icm.2018.8704105","type":"proceedings-article","created":{"date-parts":[[2019,5,2]],"date-time":"2019-05-02T22:49:41Z","timestamp":1556837381000},"page":"132-135","source":"Crossref","is-referenced-by-count":0,"title":["Framework for Developping Behavioural Models From Physical Designs"],"prefix":"10.1109","author":[{"given":"A.","family":"KOUHOUL","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Y.","family":"Karmous","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"N.","family":"BENHAMIDA","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"S.","family":"AOUINI","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"T.","family":"HADDAD","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"L.","family":"TALBI","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"year":"0","key":"ref4"},{"key":"ref3","article-title":"Extending Digital Verification Techniques for Mixed-Signal SoCswith VCS® AMS Group","author":"thibieroz","year":"2014","journal-title":"Synopsys"},{"journal-title":"Analog devices fundamentals of phase locked loops","year":"0","key":"ref10"},{"journal-title":"Mixed signal design flow master thesis","year":"2001","author":"shariat yazdi","key":"ref6"},{"year":"0","key":"ref11"},{"year":"0","key":"ref5"},{"key":"ref12","article-title":"Verilog Piecewise Linear Behavioral Modeling for Mixed- signal Validation","author":"liao","year":"2014","journal-title":"PhD dissertation"},{"year":"0","key":"ref8"},{"year":"0","key":"ref7"},{"key":"ref2","first-page":"44","article-title":"Digital Analog Design: Enabling Mixed-Signal System Validation","author":"chan","year":"2015","journal-title":"IEEE Design & Test"},{"journal-title":"Modélisation numérique de circuits analogiques\/RF\/optiques","year":"2017","author":"karmous","key":"ref9"},{"journal-title":"Towards Assertion Based Verification of Analog and Mixed Signal Designs Using PSL Department of Electrical and Computer","year":"2007","author":"al sammane","key":"ref1"}],"event":{"name":"2018 30th International Conference on Microelectronics (ICM)","start":{"date-parts":[[2018,12,16]]},"location":"Sousse, Tunisia","end":{"date-parts":[[2018,12,19]]}},"container-title":["2018 30th International Conference on Microelectronics (ICM)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8698775\/8703878\/08704105.pdf?arnumber=8704105","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,5,20]],"date-time":"2019-05-20T22:54:02Z","timestamp":1558392842000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8704105\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,12]]},"references-count":12,"URL":"https:\/\/doi.org\/10.1109\/icm.2018.8704105","relation":{},"subject":[],"published":{"date-parts":[[2018,12]]}}}