{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,5,13]],"date-time":"2026-05-13T17:39:01Z","timestamp":1778693941762,"version":"3.51.4"},"reference-count":21,"publisher":"IEEE","license":[{"start":{"date-parts":[[2019,12,1]],"date-time":"2019-12-01T00:00:00Z","timestamp":1575158400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2019,12,1]],"date-time":"2019-12-01T00:00:00Z","timestamp":1575158400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,12,1]],"date-time":"2019-12-01T00:00:00Z","timestamp":1575158400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2019,12]]},"DOI":"10.1109\/icm48031.2019.9021886","type":"proceedings-article","created":{"date-parts":[[2020,3,6]],"date-time":"2020-03-06T08:03:39Z","timestamp":1583481819000},"page":"240-243","source":"Crossref","is-referenced-by-count":12,"title":["A Novel Binary to Ternary Converter using Double Pass-Transistor Logic"],"prefix":"10.1109","author":[{"given":"Ramzi A.","family":"Jaber","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ahmad M.","family":"El-Hajj","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ali M.","family":"Haidar","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Abdallah","family":"Kassem","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Lina A.","family":"Nimri","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1016\/j.mejo.2017.12.008"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ISMVL.2018.00042"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1984.1676392"},{"key":"ref13","author":"kurt","year":"1961","journal-title":"Binary to ternary converter"},{"key":"ref14","author":"nakanishi","year":"2016","journal-title":"Pulse synthesizing circuit"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/77.403130"},{"key":"ref16","first-page":"24","article-title":"Interconnection of binary and ternary CMOS digital circuits and systems","volume":"1","author":"zlatko","year":"2010","journal-title":"MIPRO Proceedings of the 33rd International Convention"},{"key":"ref17","first-page":"19","article-title":"A novel ternary-to-binary converter in quantum-dot cellular automata","volume":"1","author":"mohsen m","year":"2012","journal-title":"IEEE Computer Society Annual Symposium on VLSI"},{"key":"ref18","doi-asserted-by":"crossref","first-page":"69","DOI":"10.1016\/j.aeue.2018.05.020","article-title":"DPL-based novel binary-to-ternary converter on CMOS technology","volume":"92","author":"aloke","year":"2018","journal-title":"AEU - International Journal of Electronics and Communications"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.1993.280071"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2016.2572206"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2019.2909707"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ACIT.2018.8672698"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2018.2789918"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1016\/j.mejo.2015.03.020"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2019.2928251"},{"key":"ref2","article-title":"Multiple valued logic: concepts and representations","author":"miller","year":"2008","journal-title":"Morgan Claypool"},{"key":"ref1","first-page":"1","article-title":"A novel very low-complexity multi-valued logic comparator in nanoelectronics","volume":"2","author":"hosseini","year":"2019","journal-title":"Springer Circuits Systems and Signal Processing"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2019.2909500"},{"key":"ref20","doi-asserted-by":"crossref","first-page":"115","DOI":"10.1080\/21681724.2016.1175031","article-title":"Benchmarking of DPL-based 8b x 8b novel wave-pipelined multiplier","volume":"5","author":"aloke","year":"2017","journal-title":"International Journal of Electronics Letters"},{"key":"ref21","first-page":"291","article-title":"Implementation of ternary circuits with binary integrated circuits","volume":"26","author":"danial","year":"1977","journal-title":"IEEE Transactions on Computers"}],"event":{"name":"2019 31st International Conference on Microelectronics (ICM)","location":"Cairo, Egypt","start":{"date-parts":[[2019,12,15]]},"end":{"date-parts":[[2019,12,18]]}},"container-title":["2019 31st International Conference on Microelectronics (ICM)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9000745\/9021274\/09021886.pdf?arnumber=9021886","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,17]],"date-time":"2022-07-17T17:53:38Z","timestamp":1658080418000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9021886\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,12]]},"references-count":21,"URL":"https:\/\/doi.org\/10.1109\/icm48031.2019.9021886","relation":{},"subject":[],"published":{"date-parts":[[2019,12]]}}}