{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,22]],"date-time":"2026-04-22T06:00:55Z","timestamp":1776837655220,"version":"3.51.2"},"reference-count":24,"publisher":"IEEE","license":[{"start":{"date-parts":[[2019,12,1]],"date-time":"2019-12-01T00:00:00Z","timestamp":1575158400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2019,12,1]],"date-time":"2019-12-01T00:00:00Z","timestamp":1575158400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,12,1]],"date-time":"2019-12-01T00:00:00Z","timestamp":1575158400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2019,12]]},"DOI":"10.1109\/icm48031.2019.9021939","type":"proceedings-article","created":{"date-parts":[[2020,3,6]],"date-time":"2020-03-06T13:03:39Z","timestamp":1583499819000},"page":"98-102","source":"Crossref","is-referenced-by-count":8,"title":["RISC-V based implementation of Programmable Logic Controller on FPGA for Industry 4.0"],"prefix":"10.1109","author":[{"given":"Hossameldin","family":"Eassa","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ihab","family":"Adly","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hanady H.","family":"Issa","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","author":"chmiel","year":"2010","journal-title":"A FPGA-Based Bit-Word PLC CPUs Development Platform"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1016\/j.isatra.2014.08.019"},{"key":"ref12","author":"chmiel","year":"2015","journal-title":"IEC 61131–3-based PLC Implemented by means of FPGA"},{"key":"ref13","article-title":"IEC control specification to HDL synthesis: Considerations for implementing PLC on FPGA and scope for research","author":"patil","year":"2010","journal-title":"8th International Conference on Control Automation Robotics and Vision"},{"key":"ref14","article-title":"Novel integrated development environment for implementing PLC on FPGA by converting ladder diagram to synthesizable VHDL code","author":"patil","year":"2010","journal-title":"8th International Conference on Control Automation Robotics and Vision"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1002\/tee.20670"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1016\/j.micpro.2016.02.003"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.2478\/v10177-012-0012-8"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.15598\/aeee.v12i5.1134"},{"key":"ref19","article-title":"Transforming Ladder Logic to Verilog for FPGA Realization of Programmable Logic Controllers","author":"brunner","year":"2017","journal-title":"2017 World Congress in Computer Science Computer Engineering & Applied"},{"key":"ref4","author":"langmann","year":"2016","journal-title":"A PLC as an Industry 4 0 component"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1016\/j.micpro.2015.11.001"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1016\/S1383-7621(97)00011-8"},{"key":"ref5","first-page":"18","article-title":"A Cyber-Physical Systems architecture for Industry 4.0-based manufacturing systems","volume":"3","author":"jay","year":"2014","journal-title":"Manufacturing Letters"},{"key":"ref8","author":"kim","year":"1999","journal-title":"A translation method for ladder diagram with application to a manufacturing process"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1016\/0141-9331(96)84161-5"},{"key":"ref2","first-page":"138","volume":"46","author":"czerwinski","year":"2013","journal-title":"FPGA Implementation of Programmable Logic Controller Compliant with EN 61131–3"},{"key":"ref1","year":"0","journal-title":"Programmable controllers - Part 3 Programming languages"},{"key":"ref9","author":"chmiel","year":"2011","journal-title":"Central Processing Units for PLC implementation in Virtex-4 FPGA"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/ISIE.2017.8001426"},{"key":"ref22","author":"skordal","year":"0","journal-title":"A simple RISC-V processor for use in FPGA designs"},{"key":"ref21","first-page":"64","article-title":"FPGA Implementations of Ladder Diagrams","volume":"7","author":"bergmann","year":"2013","journal-title":"Mathematical Models and Methods in Applied Sciences"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/ICICTA.2017.87"},{"key":"ref23","author":"li","year":"2004","journal-title":"ECOMIPS an economic MIPS CPU design on FPGA"}],"event":{"name":"2019 31st International Conference on Microelectronics (ICM)","location":"Cairo, Egypt","start":{"date-parts":[[2019,12,15]]},"end":{"date-parts":[[2019,12,18]]}},"container-title":["2019 31st International Conference on Microelectronics (ICM)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9000745\/9021274\/09021939.pdf?arnumber=9021939","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,17]],"date-time":"2022-07-17T21:50:00Z","timestamp":1658094600000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9021939\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,12]]},"references-count":24,"URL":"https:\/\/doi.org\/10.1109\/icm48031.2019.9021939","relation":{},"subject":[],"published":{"date-parts":[[2019,12]]}}}