{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,23]],"date-time":"2024-10-23T07:35:09Z","timestamp":1729668909895,"version":"3.28.0"},"reference-count":13,"publisher":"IEEE Comput. Soc","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/icpads.2002.1183382","type":"proceedings-article","created":{"date-parts":[[2003,6,26]],"date-time":"2003-06-26T15:35:00Z","timestamp":1056641700000},"page":"83-90","source":"Crossref","is-referenced-by-count":2,"title":["Organization of shared memory with synchronization for multiprocessor-on-a-chip"],"prefix":"10.1109","author":[{"given":"A.","family":"Yamawaki","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"M.","family":"Iwane","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","first-page":"1457","article-title":"The Effect of Counter and Blocking for a Communication and Synchronization Memory","volume":"j84 d i","author":"yamawaki","year":"2001","journal-title":"IEICE Trans"},{"journal-title":"Intel Corp Intel 486 Microprocessor and Related Products Intel Corp","year":"1995","key":"ref11"},{"journal-title":"Computer Architecture and Parallel Processing","year":"1986","author":"hwang","key":"ref12"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/356887.356892"},{"key":"ref4","doi-asserted-by":"crossref","DOI":"10.1109\/ISCA.1999.765935","article-title":"Maps: A Compiler-Managed Memory Sytem for Raw Machines","author":"barua","year":"1999","journal-title":"Proc Int Symp Computer Architecture"},{"key":"ref3","first-page":"12","article-title":"Space-Efficiet Scheduling of Parallelism with Synchronization Variables","author":"blelloch","year":"1997","journal-title":"Proc of the 9th Annual ACM Symp on Parallel Algorithms and Architectures"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/12.795219"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/40.848474"},{"key":"ref8","first-page":"253","article-title":"Design of cache memories for multi-threaded dataflow architecture","author":"kavi","year":"1995","journal-title":"Proceedings 22nd Annual International Symposium on Computer Architecture ISCA"},{"key":"ref7","doi-asserted-by":"crossref","DOI":"10.1145\/342001.339696","article-title":"Pinanha: A Scalable Architecture Based on Single-Chip Multiprocessing","author":"barroso","year":"2000","journal-title":"Proc of Int Symp on Computer Architecture"},{"key":"ref2","doi-asserted-by":"crossref","first-page":"598","DOI":"10.1145\/69558.69562","article-title":"I-Structure: Data Structures for Parallel Computing","volume":"11","author":"nikhil","year":"1989","journal-title":"ACM Trans Prog Lang Syst"},{"key":"ref1","first-page":"317","article-title":"Tagged communication and synchronization memory for multiprocessor-on-a-chip","volume":"j83 d i","author":"iwane","year":"2000","journal-title":"IEICE Trans"},{"key":"ref9","article-title":"Performance Impacts of Caching I-Structure Data on Frame-Based Multithreaded Processing","author":"kim","year":"1997","journal-title":"Proc HPC Asia'97"}],"event":{"name":"Ninth International Conference on Parallel and Distributed Systems","acronym":"ICPADS-02","location":"Taiwan, China"},"container-title":["Ninth International Conference on Parallel and Distributed Systems, 2002. Proceedings."],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8425\/26545\/01183382.pdf?arnumber=1183382","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,6,8]],"date-time":"2021-06-08T08:58:19Z","timestamp":1623142699000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1183382\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":13,"URL":"https:\/\/doi.org\/10.1109\/icpads.2002.1183382","relation":{},"subject":[]}}