{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,29]],"date-time":"2025-09-29T12:02:58Z","timestamp":1759147378389},"reference-count":21,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2007,12]]},"DOI":"10.1109\/icpads.2007.4447739","type":"proceedings-article","created":{"date-parts":[[2008,2,15]],"date-time":"2008-02-15T17:32:18Z","timestamp":1203096738000},"page":"1-8","source":"Crossref","is-referenced-by-count":6,"title":["Virtual Exclusion: An architectural approach to reducing leakage energy in caches for multiprocessor systems"],"prefix":"10.1109","author":[{"given":"M.","family":"Ghosh","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"H.-H.S.","family":"Lee","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/507052.507055"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/1088149.1088154"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/605397.605420"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/1016720.1016757"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/22.981277"},{"key":"ref15","doi-asserted-by":"crossref","first-page":"262","DOI":"10.1145\/1165573.1165636","article-title":"Process variation aware cache leakage management","author":"meng","year":"2006","journal-title":"Proceedings of the 2006 International Symposium on Low Power Electronics and Design"},{"key":"ref16","doi-asserted-by":"crossref","first-page":"293","DOI":"10.1145\/280756.280939","article-title":"A low power SRAM using auto-backgate-controlled MT-CMOS","author":"nii","year":"1998","journal-title":"Proceedings 1998 International Symposium on Low Power Electronics and Design (IEEE Cat No 98TH8379) LPE"},{"key":"ref17","doi-asserted-by":"crossref","first-page":"90","DOI":"10.1109\/LPE.2000.155259","article-title":"gated-v\/sub dd\/: a circuit technique to reduce leakage in deep-submicron cache memories","author":"powell","year":"2000","journal-title":"ISLPED 00 the 2000 International Symposium on Low Power Electronics and Design (Cat No 00TH8514) LPE-00"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/513918.513941"},{"journal-title":"Pentium Pro Processor System Architecture MindShare Inc","year":"1997","author":"shanley","key":"ref19"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1999.809463"},{"journal-title":"AMD Athlon Processor Architecture","year":"2000","key":"ref3"},{"key":"ref6","article-title":"Network-Oriented Full-System Simulation using M5","author":"binkert","year":"2003","journal-title":"Workshop Computer Architecture Evaluation Using Commercial Workloads"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1988.5212"},{"key":"ref8","article-title":"Drowsy caches: Simple techniques for reducing leakage power","author":"flautner","year":"2002","journal-title":"Proc of ISCA-29"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2003.1253183"},{"year":"2004","key":"ref2"},{"year":"0","key":"ref1"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/507052.507055"},{"key":"ref20","doi-asserted-by":"crossref","first-page":"24","DOI":"10.1109\/ISCA.1995.524546","article-title":"The SPLASH-2 programs: characterization and methodological considerations","author":"woo","year":"1995","journal-title":"Proceedings 22nd Annual International Symposium on Computer Architecture ISCA"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2001.903259"}],"event":{"name":"2007 International Conference on Parallel and Distributed Systems","start":{"date-parts":[[2007,12,5]]},"location":"Hsinchu","end":{"date-parts":[[2007,12,7]]}},"container-title":["2007 International Conference on Parallel and Distributed Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4447704\/4447779\/04447739.pdf?arnumber=4447739","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,5,16]],"date-time":"2023-05-16T14:22:33Z","timestamp":1684246953000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/4447739\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2007,12]]},"references-count":21,"URL":"https:\/\/doi.org\/10.1109\/icpads.2007.4447739","relation":{},"subject":[],"published":{"date-parts":[[2007,12]]}}}