{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,9,30]],"date-time":"2026-09-30T18:14:12Z","timestamp":1790792052692,"version":"4.1.0"},"reference-count":22,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2016,10]]},"DOI":"10.1109\/icrc.2016.7738698","type":"proceedings-article","created":{"date-parts":[[2016,11,10]],"date-time":"2016-11-10T21:39:45Z","timestamp":1478813985000},"page":"1-8","source":"Crossref","is-referenced-by-count":35,"title":["DRC<sup>2<\/sup>: Dynamically Reconfigurable Computing Circuit based on memory architecture"],"prefix":"10.1109","author":[{"given":"Kaya Can","family":"Akyel","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Henri-Pierre","family":"Charles","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Julien","family":"Mottin","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Bastien","family":"Giraud","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Gregory","family":"Suraci","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Sebastien","family":"Thuries","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Jean-Philippe","family":"Noel","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"crossref","first-page":"869","DOI":"10.1145\/775832.776051","article-title":"Intelligent SRAM (ISRAM) for Improved Embedded System Performance","author":"jain","year":"2003","journal-title":"DAC"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2013.2282132"},{"key":"ref12","first-page":"1718","article-title":"Memristor based computation-in-memory architecture for data-intesive applications","author":"hamdioui","year":"2015"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2014.8"},{"key":"ref14","first-page":"161","article-title":"Video-Active RAM: A Processor-in-Memory Architecture for Video Coding Applications","year":"2010","journal-title":"ISCA"},{"key":"ref15","first-page":"1009","article-title":"A 28 nm Configurable Memory (TCAM\/BCAM\/SRAM) Using Push-Rule 6T Bit Cell Enabling Logic-in-Memory","volume":"51","year":"2016","journal-title":"IEEE JSSC"},{"key":"ref16","first-page":"728","article-title":"A 0.5V 25MHz lmW 256kb MTCMOS\/SOI SRAM for solar-power-operated portable personal digital equipment-sure write operation by using step-down negatively overdriven bit-line scheme","volume":"41","year":"2006","journal-title":"JSSC"},{"key":"ref17","first-page":"1859","article-title":"Modeling of failure probability and statistical design of SRAM array for yield enhancement in nanoscaled CMOS","volume":"24","year":"2005","journal-title":"IEEE TCAD"},{"key":"ref18","article-title":"The Connectino Machine","author":"hillis","year":"1989"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1145\/319838.319870"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2010.5433924"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2014.6865601"},{"key":"ref6","article-title":"Power Programmability, and Granularity","author":"dally","year":"2011","journal-title":"keynote presentation in IPDPS"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2014.6757323"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/2.375174"},{"key":"ref7","year":"2015"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/218864.218865"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/216585.216588"},{"key":"ref9","first-page":"1","article-title":"A 3D-Stacked Logic-in-Memory Accelerator for Application-Specific Data Intensive Computing","year":"2013","journal-title":"3DIC"},{"key":"ref20","article-title":"Occupancy grids: a stochastic representation for active robot perception","author":"elfes","year":"1990"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1177\/0278364906061158"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/ICRA.2016.7487330"}],"event":{"name":"2016 IEEE International Conference on Rebooting Computing (ICRC)","location":"San Diego, CA, USA","start":{"date-parts":[[2016,10,17]]},"end":{"date-parts":[[2016,10,19]]}},"container-title":["2016 IEEE International Conference on Rebooting Computing (ICRC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7733896\/7738669\/07738698.pdf?arnumber=7738698","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,12]],"date-time":"2025-06-12T10:38:56Z","timestamp":1749724736000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7738698\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,10]]},"references-count":22,"URL":"https:\/\/doi.org\/10.1109\/icrc.2016.7738698","relation":{},"subject":[],"published":{"date-parts":[[2016,10]]}}}