{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,22]],"date-time":"2024-10-22T23:17:56Z","timestamp":1729639076258,"version":"3.28.0"},"reference-count":21,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/icsmc.2005.1571742","type":"proceedings-article","created":{"date-parts":[[2006,1,18]],"date-time":"2006-01-18T23:42:54Z","timestamp":1137627774000},"page":"3823-3827","source":"Crossref","is-referenced-by-count":2,"title":["Using FPGA Technology Towards the Design of an Adaptive Fault Tolerant Framework"],"prefix":"10.1109","volume":"4","author":[{"given":"S.","family":"Erdogan","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"J.L.","family":"Gersting","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"T.","family":"Shaneyfelt","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"E.L.","family":"Duke","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","article-title":"The Time-Triggered Architecture","author":"kopetz","year":"2002","journal-title":"IEEE Special Issue on Modeling and Design of Embedded Software"},{"doi-asserted-by":"publisher","key":"ref11","DOI":"10.1007\/978-94-015-9884-2"},{"doi-asserted-by":"publisher","key":"ref12","DOI":"10.1109\/HICSS.1989.48118"},{"doi-asserted-by":"publisher","key":"ref13","DOI":"10.1145\/358234.358246"},{"year":"2000","author":"xu","article-title":"A Generic Implementation Approach to Concurrent Fault-Tolerant Software","key":"ref14"},{"year":"1995","author":"butler","article-title":"Techniques for Modeling the Reliability of Fault-Tolerant Systems With the Markov State-Space Approach","key":"ref15"},{"key":"ref16","article-title":"The Teramac Custom Computer: Extending the Limits with Defect Tolerance","author":"culbertson","year":"1996","journal-title":"Proc IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems"},{"key":"ref17","doi-asserted-by":"crossref","first-page":"141","DOI":"10.1007\/3-540-63465-7_219","article-title":"Partial Reconfiguration of FGPA Mapped Designs with Applicatios to Fault Tolerance and Yield Enhancement","author":"emmert","year":"1997","journal-title":"The 7th Annual Workshop on Field Programmable Logic and Applications"},{"key":"ref18","doi-asserted-by":"crossref","first-page":"15","DOI":"10.1109\/12.656073","article-title":"Methodologies for Tolerating Logic and Interconnect Faults in FPGAs","author":"hanchek","year":"1998","journal-title":"IEEE Trans Computers Special Issue on Dependable Computing"},{"doi-asserted-by":"publisher","key":"ref19","DOI":"10.1145\/503074.503076"},{"key":"ref4","first-page":"614","article-title":"Programming a Reconfigurable Platform for Neural Network Simulations","author":"erdogan","year":"2004","journal-title":"6th IASTED International Conference on Signal and Image Processing"},{"key":"ref3","doi-asserted-by":"crossref","first-page":"39","DOI":"10.1109\/52.28122","article-title":"V & V of Flight and Mission Critical Software","volume":"6","author":"eugene","year":"1989","journal-title":"IEEE Software"},{"key":"ref6","article-title":"Stream Computations Organized for Reconfigurable Execution (SCORE): Introduction and Tutorial","author":"caspi","year":"2000","journal-title":"Proc Int Conf Field Programmable Logic and Applications"},{"key":"ref5","article-title":"Programming a Reconfigurable Platform for Neural Network Simulations","author":"erdogan","year":"2004","journal-title":"Proc of the IASTED International Conference on Circuits Signals and Systems"},{"key":"ref8","doi-asserted-by":"crossref","DOI":"10.1109\/FPGA.1997.624600","article-title":"Garp: A MIPS Processor with a Reconfigurable Coprocessor","author":"hauser","year":"1997","journal-title":"Proc of the IEEE Symposium on Field-Programmable Custom Computing Machines"},{"year":"2000","journal-title":"Proc SPIE","article-title":"Framework for architecture-independent run-time reconfigurable applications","key":"ref7"},{"key":"ref2","article-title":"Reconfiguration Control for Dynamically Reconfigurable Systems","author":"carvalho","year":"2004","journal-title":"Proc 19th Conf Design of Circuits and Integr Syst"},{"key":"ref1","first-page":"3","article-title":"Automated design synthesis and partitioning for adaptive reconfigurable hardware, Hardware implementation of intelligent systems","author":"vemuri","year":"2001"},{"doi-asserted-by":"publisher","key":"ref9","DOI":"10.1007\/3-540-45177-3_6"},{"doi-asserted-by":"publisher","key":"ref20","DOI":"10.1145\/354880.354889"},{"doi-asserted-by":"publisher","key":"ref21","DOI":"10.1109\/HICSS.2005.194"}],"event":{"name":"2005 IEEE International Conference on Systems, Man and Cybernetics","location":"Waikoloa, HI, USA"},"container-title":["2005 IEEE International Conference on Systems, Man and Cybernetics"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/10498\/33257\/01571742.pdf?arnumber=1571742","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,4,15]],"date-time":"2019-04-15T10:24:54Z","timestamp":1555323894000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1571742\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":21,"URL":"https:\/\/doi.org\/10.1109\/icsmc.2005.1571742","relation":{},"subject":[]}}