{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,30]],"date-time":"2024-10-30T03:20:53Z","timestamp":1730258453476,"version":"3.28.0"},"reference-count":14,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011,10]]},"DOI":"10.1109\/icsmc.2011.6084133","type":"proceedings-article","created":{"date-parts":[[2011,11,23]],"date-time":"2011-11-23T21:53:12Z","timestamp":1322085192000},"page":"3084-3089","source":"Crossref","is-referenced-by-count":1,"title":["DoE applied to two-level memory hierarchies for energy consumption reduction"],"prefix":"10.1109","author":[{"given":"A. G.","family":"Silva-Filho","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"F. R.","family":"Cordeiro","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/268806.268810"},{"key":"ref11","article-title":"eCACTI: An Enhanced Power Estimation Model for On-chip Caches","author":"dutt","year":"2004","journal-title":"TR 04&#x2013;28 set"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1016\/j.asoc.2009.11.029"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/SBAC-PAD.2010.40"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2008.2002459"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1007\/11847083_8"},{"key":"ref3","first-page":"164","article-title":"Cache configuration exploration on prototyping platforms","volume":"0","author":"zhang","year":"0","journal-title":"14th IEEE Interational Workshop on Rapid System Prototyping"},{"key":"ref6","first-page":"208","article-title":"Automatic Tuning of Two-Level Caches to Embedded Aplications","author":"gordon-ross","year":"2004","journal-title":"DATE"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/SBAC-PAD.2008.9"},{"key":"ref8","first-page":"660","author":"montgomery","year":"1997","journal-title":"Design and Analysis of Experiments"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/SBAC-PAD.2007.14"},{"key":"ref2","article-title":"Compiler-Directed Scratch Pad Memory Hierarchy Design and Management","author":"kandemir","year":"0","journal-title":"Proc Design Automation Conf (DAC '02)"},{"journal-title":"Advanced Memory Optimization Techniques for Low-Power Embedded Processors","year":"2007","author":"verma","key":"ref1"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/WWC.2001.990739"}],"event":{"name":"2011 IEEE International Conference on Systems, Man and Cybernetics - SMC","start":{"date-parts":[[2011,10,9]]},"location":"Anchorage, AK, USA","end":{"date-parts":[[2011,10,12]]}},"container-title":["2011 IEEE International Conference on Systems, Man, and Cybernetics"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/6070513\/6083622\/06084133.pdf?arnumber=6084133","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,21]],"date-time":"2017-03-21T13:56:39Z","timestamp":1490104599000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6084133\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,10]]},"references-count":14,"URL":"https:\/\/doi.org\/10.1109\/icsmc.2011.6084133","relation":{},"subject":[],"published":{"date-parts":[[2011,10]]}}}