{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,7]],"date-time":"2024-09-07T20:05:22Z","timestamp":1725739522363},"reference-count":25,"publisher":"IEEE","license":[{"start":{"date-parts":[[2023,10,11]],"date-time":"2023-10-11T00:00:00Z","timestamp":1696982400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2023,10,11]],"date-time":"2023-10-11T00:00:00Z","timestamp":1696982400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2023,10,11]]},"DOI":"10.1109\/icstcc59206.2023.10308483","type":"proceedings-article","created":{"date-parts":[[2023,11,10]],"date-time":"2023-11-10T18:49:18Z","timestamp":1699642158000},"page":"410-415","source":"Crossref","is-referenced-by-count":1,"title":["Selective High-Latency Arithmetic Instruction Reuse in Multicore Processors"],"prefix":"10.1109","author":[{"given":"Claudiu","family":"Buduleci","sequence":"first","affiliation":[{"name":"Lucian Blaga University of Sibiu,Computer Science and Electrical Engineering Department,Sibiu,Romania"}]},{"given":"Arpad","family":"Gellert","sequence":"additional","affiliation":[{"name":"Lucian Blaga University of Sibiu,Computer Science and Electrical Engineering Department,Sibiu,Romania"}]},{"given":"Adrian","family":"Florea","sequence":"additional","affiliation":[{"name":"Lucian Blaga University of Sibiu,Computer Science and Electrical Engineering Department,Sibiu,Romania"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/iccc54292.2022.9805869"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/2063384.2063454"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/384286.264200"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/hpca.1999.744342"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1016\/j.sysarc.2008.11.002"},{"volume-title":"Advanced Prediction Methods Integrated Into Speculative Computer Architectures","year":"2008","author":"Gellert","key":"ref6"},{"volume-title":"Beyond the limits of modern processors","year":"2008","author":"Gellert","key":"ref7"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/3373376.3378520"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/hpca.2018.00041"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/3429440"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1002\/cpe.5403"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/southeastcon42311.2019.9020648"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1002\/cpe.7204"},{"key":"ref14","article-title":"Saving RNN Computations with a Neuron-Level Fuzzy Memoization Scheme","author":"Silfa","year":"2022","journal-title":"arXiv"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/hpca.2010.5416635"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2010.5416636"},{"article-title":"Flexible Timing Simulation of RISC-V Processors with Sniper","volume-title":"Second Workshop on Computer Architecture Research with RISC-V","author":"Mallya","key":"ref17"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/2024716.2024718"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/isca.1995.524546"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/iiswc55918.2022.00015"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1145\/1186736.1186737"},{"key":"ref22","article-title":"Benchmarking Modern Multiprocessors","author":"Bienia","year":"2011","journal-title":"Princeton University"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669172"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/icstcc.2014.6982386"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1145\/2629677"}],"event":{"name":"2023 27th International Conference on System Theory, Control and Computing (ICSTCC)","start":{"date-parts":[[2023,10,11]]},"location":"Timisoara, Romania","end":{"date-parts":[[2023,10,13]]}},"container-title":["2023 27th International Conference on System Theory, Control and Computing (ICSTCC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/10305866\/10308427\/10308483.pdf?arnumber=10308483","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,3,2]],"date-time":"2024-03-02T13:27:57Z","timestamp":1709386077000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10308483\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,10,11]]},"references-count":25,"URL":"https:\/\/doi.org\/10.1109\/icstcc59206.2023.10308483","relation":{},"subject":[],"published":{"date-parts":[[2023,10,11]]}}}