{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,26]],"date-time":"2026-02-26T15:23:36Z","timestamp":1772119416324,"version":"3.50.1"},"reference-count":5,"publisher":"IEEE","license":[{"start":{"date-parts":[[2022,10,28]],"date-time":"2022-10-28T00:00:00Z","timestamp":1666915200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2022,10,28]],"date-time":"2022-10-28T00:00:00Z","timestamp":1666915200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2022,10,28]]},"DOI":"10.1109\/icta56932.2022.9963017","type":"proceedings-article","created":{"date-parts":[[2022,12,2]],"date-time":"2022-12-02T21:06:48Z","timestamp":1670015208000},"page":"15-16","source":"Crossref","is-referenced-by-count":2,"title":["Low-Latency FPGA Design and Implementation of Hermitian Matrix Inversion Based on Partitioned Systolic Array for Massive MIMO"],"prefix":"10.1109","author":[{"given":"Ke","family":"Han","sequence":"first","affiliation":[{"name":"School of Electronic Engineering, Beijing University of Posts and Telecommunications,Beijing,China,100876"}]},{"given":"Daokun","family":"Li","sequence":"additional","affiliation":[{"name":"School of Electronic Engineering, Beijing University of Posts and Telecommunications,Beijing,China,100876"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TSP.2021.3064781"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TIE.2020.2994865"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2020.3034437"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/LASCAS51355.2021.9459171"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TVT.2022.3172950"}],"event":{"name":"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","location":"Xi'an, China","start":{"date-parts":[[2022,10,28]]},"end":{"date-parts":[[2022,10,30]]}},"container-title":["2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9962812\/9962965\/09963017.pdf?arnumber=9963017","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,12,19]],"date-time":"2022-12-19T20:00:58Z","timestamp":1671480058000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9963017\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,10,28]]},"references-count":5,"URL":"https:\/\/doi.org\/10.1109\/icta56932.2022.9963017","relation":{},"subject":[],"published":{"date-parts":[[2022,10,28]]}}}