{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,30]],"date-time":"2024-10-30T03:52:14Z","timestamp":1730260334638,"version":"3.28.0"},"reference-count":15,"publisher":"IEEE Comput. Soc","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/icvd.2003.1183120","type":"proceedings-article","created":{"date-parts":[[2003,8,27]],"date-time":"2003-08-27T11:38:00Z","timestamp":1061984280000},"page":"91-96","source":"Crossref","is-referenced-by-count":2,"title":["A fast macro based compilation methodology for partially reconfigurable FPGA designs"],"prefix":"10.1109","author":[{"given":"M.","family":"Handa","sequence":"first","affiliation":[]},{"given":"R.","family":"Radhakrishnan","sequence":"additional","affiliation":[]},{"given":"M.","family":"Mukherjee","sequence":"additional","affiliation":[]},{"given":"R.","family":"Vemuri","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"journal-title":"Formal Synthesis Formal Assertions Based Verification in a High-level Synthesis System","year":"1998","author":"narasimhan","key":"ref10"},{"key":"ref11","article-title":"Theorem Proving Guided Development of Formal Assertions in a Resource-Constrained Scheduler for High-Level Synthesis","volume":"19","author":"narasimhan","year":"2001","journal-title":"Formal Methods Syst Design (FMSD)"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/296399.296463"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/503048.503081"},{"journal-title":"Sblox A Language for Digital System Synthesis Technical Report No 258\/05\/01\/ECECS","year":"2000","author":"vemuri","key":"ref14"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/FPGA.1995.477415"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/FPGA.1998.707919"},{"journal-title":"JBits Reference Manual Release 2 8","year":"2001","key":"ref3"},{"key":"ref6","article-title":"JBits: A Java-based Interface for Reconfigurable Computing","author":"guccione","year":"1999","journal-title":"2nd Annual Military and Aerospace Applications of Programmable Devices and Technologies Conference"},{"journal-title":"Data Structures and Algorithms in Java","year":"2001","author":"goodrich","key":"ref5"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/329166.329190"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/FPGA.1995.477412"},{"journal-title":"SLAAC-1V Reference Manual","year":"2000","key":"ref2"},{"journal-title":"Virtex 2 5v Field Programmable Gate Arrays Reference Manual","year":"1999","key":"ref1"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/FPGA.1997.624605"}],"event":{"name":"16th International Conference on VLSI Design. Concurrently with the 2nd International Conference on Embedded Systems Design","acronym":"ICVD-03","location":"New Delhi, India"},"container-title":["16th International Conference on VLSI Design, 2003. Proceedings."],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8427\/26547\/01183120.pdf?arnumber=1183120","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,13]],"date-time":"2017-03-13T18:28:08Z","timestamp":1489429688000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1183120\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":15,"URL":"https:\/\/doi.org\/10.1109\/icvd.2003.1183120","relation":{},"subject":[]}}