{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,1]],"date-time":"2025-11-01T09:06:34Z","timestamp":1761987994734},"reference-count":16,"publisher":"IEEE Comput. Soc","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/icvd.2004.1260929","type":"proceedings-article","created":{"date-parts":[[2004,6,21]],"date-time":"2004-06-21T17:52:40Z","timestamp":1087840360000},"page":"228-233","source":"Crossref","is-referenced-by-count":10,"title":["A new technique for leakage reduction in CMOS circuits using self-controlled stacked transistors"],"prefix":"10.1109","author":[{"given":"N.","family":"Hanchate","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"N.","family":"Ranganathan","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"journal-title":"Principles of CMOS VLSI Design A Systems Perspective","year":"1993","author":"weste","key":"ref10"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/288548.289076"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/4.509853"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/383082.383132"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/92.994980"},{"key":"ref15","article-title":"MUS Scaling: Transistor Challenges for the 21st century","author":"thompson","year":"1998","journal-title":"Intel Technology Journal Q3"},{"key":"ref16","doi-asserted-by":"crossref","first-page":"139","DOI":"10.1145\/313817.313900","article-title":"Low power synthesis of dual threshold voltage CMOS VLSI circuits","author":"sundararajan","year":"1999","journal-title":"Proceedings 1999 International Symposium on Low Power Electronics and Design (Cat No 99TH8477) LPE"},{"journal-title":"SIS A system for sequential circuit synthesis","year":"1992","author":"sentovich","key":"ref4"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2002.994881"},{"key":"ref6","first-page":"409","article-title":"Transistor Sizing Issues and Tool for Multi-Threshold CMOS Technology","author":"kao","year":"0","journal-title":"Proc of 34th DAC"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1984.1052168"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/92.988724"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.1997.606670"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1987.1052773"},{"key":"ref1","article-title":"Covering Strategies for Library Free Technology Mapping","author":"reis","year":"1998","journal-title":"Proc of the XII Brazilian Symposium on Integrated Circuits and Systems Design"},{"key":"ref9","doi-asserted-by":"crossref","first-page":"90","DOI":"10.1109\/LPE.2000.155259","article-title":"gated-v\/sub dd\/: a circuit technique to reduce leakage in deep-submicron cache memories","author":"powell","year":"2000","journal-title":"ISLPED 00 the 2000 International Symposium on Low Power Electronics and Design (Cat No 00TH8514) LPE-00"}],"event":{"name":". 17th International Conference on VLSI Design","acronym":"ICVD-04","location":"Mumbai, India"},"container-title":["17th International Conference on VLSI Design. Proceedings."],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8911\/28180\/01260929.pdf?arnumber=1260929","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,16]],"date-time":"2017-06-16T04:12:11Z","timestamp":1497586331000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1260929\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":16,"URL":"https:\/\/doi.org\/10.1109\/icvd.2004.1260929","relation":{},"subject":[]}}