{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,26]],"date-time":"2025-09-26T13:07:24Z","timestamp":1758892044517,"version":"3.28.0"},"reference-count":12,"publisher":"IEEE Comput. Soc","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/icvd.2004.1260969","type":"proceedings-article","created":{"date-parts":[[2004,6,21]],"date-time":"2004-06-21T21:52:40Z","timestamp":1087854760000},"page":"493-498","source":"Crossref","is-referenced-by-count":8,"title":["Open defects detection within 6T SRAM cells using a No Write Recovery Test Mode"],"prefix":"10.1109","author":[{"family":"Josh Yang","sequence":"first","affiliation":[]},{"family":"Baosheng Wang","sequence":"additional","affiliation":[]},{"given":"A.","family":"Ivanov","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.4218\/etrij.01.0101.0205"},{"key":"ref3","doi-asserted-by":"crossref","first-page":"106","DOI":"10.1109\/VTEST.1998.670856","article-title":"IDDQ testing of opens in CMOS SRAMs","author":"champac","year":"1998","journal-title":"16th IEEE VLSI Test Symposium"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1987.1052809"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1049\/el:20000855"},{"key":"ref11","doi-asserted-by":"crossref","first-page":"937","DOI":"10.1109\/ISCAS.1995.519919","article-title":"Static Noise Margin and Soft-Error Rate Simulations for Thin Film Transistor Cell Stability in a 4 Mbit SRAM Design","volume":"2","author":"lee","year":"1995","journal-title":"1995 IEEE International Symposium on Circuits and Systems"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1996.556976"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2002.1033788"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1983.1051965"},{"key":"ref7","first-page":"862","article-title":"Cache Ram Inductive Fault Analysis With Fab Defect Modeling","author":"mark","year":"1998","journal-title":"Proceedings of International Test Conference"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.1992.229919"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2000.893615"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/MTDT.2002.1029756"}],"event":{"name":". 17th International Conference on VLSI Design","acronym":"ICVD-04","location":"Mumbai, India"},"container-title":["17th International Conference on VLSI Design. Proceedings."],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8911\/28180\/01260969.pdf?arnumber=1260969","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,1,13]],"date-time":"2024-01-13T18:00:28Z","timestamp":1705168828000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1260969\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":12,"URL":"https:\/\/doi.org\/10.1109\/icvd.2004.1260969","relation":{},"subject":[]}}