{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,30]],"date-time":"2024-10-30T04:16:33Z","timestamp":1730261793375,"version":"3.28.0"},"reference-count":41,"publisher":"IEEE","license":[{"start":{"date-parts":[[2019,9,1]],"date-time":"2019-09-01T00:00:00Z","timestamp":1567296000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2019,9,1]],"date-time":"2019-09-01T00:00:00Z","timestamp":1567296000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,9,1]],"date-time":"2019-09-01T00:00:00Z","timestamp":1567296000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2019,9]]},"DOI":"10.1109\/idaacs.2019.8924435","type":"proceedings-article","created":{"date-parts":[[2019,12,6]],"date-time":"2019-12-06T10:26:29Z","timestamp":1575627989000},"page":"239-243","source":"Crossref","is-referenced-by-count":0,"title":["A Method of the Result Preparation in Addition-Based Circuits"],"prefix":"10.1109","author":[{"given":"Oleksandr","family":"Drozd","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Anatoliy","family":"Sachenko","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Konrad","family":"Grzeszczyk","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Nadiia","family":"Vasylkiv","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Julia","family":"Drozd","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Iryna","family":"Turchenko","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Andrij","family":"Karachka","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"journal-title":"The Quartus II TimeQuest Timing Analyzer","year":"0","key":"ref39"},{"journal-title":"Cyclone II Device Handbook","year":"0","key":"ref38"},{"journal-title":"DESIGN OF SINGLE PRECISION FLOAT ADDER (32-BIT NUMBERS) ACCORDIN TO IEEE 754 STANDARD USING VHDL","year":"2012","author":"castillo","key":"ref33"},{"year":"0","key":"ref32"},{"year":"0","key":"ref31"},{"journal-title":"NVIDIA CUDA Compute Unified Device Architecture Programming Guide","first-page":"113","year":"2007","key":"ref30"},{"journal-title":"Quartus II Handbook Version 13 1","year":"0","key":"ref37"},{"journal-title":"Altera FPGA Architecture","year":"0","key":"ref36"},{"key":"ref35","first-page":"252","article-title":"Advanced FPGA Architectures for Efficient Implementation of Computation Intensive Algorithms: A State-of-the-Art Review","volume":"1","author":"qasim","year":"2009","journal-title":"MASAUM Journal of Computing"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2001.915042"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/SSST.2003.1194605"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/IOLTS.2006.61"},{"key":"ref11","first-page":"267","article-title":"Diversity in Open Source Intrusion Detection Systems","volume":"8666","author":"asad","year":"2014","journal-title":"Computer Safety Reliability and Security Lecture Notes in Computer Science"},{"year":"2007","key":"ref12"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/IDAACS.2015.7341415"},{"key":"ref14","first-page":"654","article-title":"Improving of a Circuit Checkability and Trustworthiness of Data Processing Results in LUT-based FPGA Components of Safety-Related Systems","volume":"1844","author":"drozd","year":"0","journal-title":"CEUR Workshop Proceedings"},{"journal-title":"Google Search Engine","year":"0","key":"ref15"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1016\/S0169-7552(98)00110-X"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/IRETELC.1962.5407919"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2010.2101621"},{"journal-title":"Intel Quartus Prime Standard Edition User Guide Getting Started","year":"0","key":"ref19"},{"journal-title":"DWFC Flexible Floating Point Overview","first-page":"1","year":"2016","key":"ref28"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TDSC.2004.40"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/IDAACS.2013.6662656"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/12.980005"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1016\/j.jsr.2013.05.003"},{"key":"ref29","first-page":"72","article-title":"Parallelism and Complexity of a Small-World Network Model","volume":"15","author":"hiromoto","year":"0","journal-title":"International Journal of Computing"},{"year":"2010","key":"ref5"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ICIEAM.2016.7911431"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1201\/b17555"},{"journal-title":"Library classification schemes An overview Shodhganga a reservoir of Indian theses","year":"0","key":"ref2"},{"key":"ref9","first-page":"507","article-title":"Computer's analysis method and reliability assessment of fault-tolerance operation of information systems","volume":"1356","author":"atamanyuk","year":"0","journal-title":"CEUR Workshop Proceedings"},{"journal-title":"UG-01063 17 1","article-title":"Intel FPGA Integer Arithmetic IP Cores User Guide","year":"2017","key":"ref1"},{"journal-title":"LogiCORE IP floating-point operator v7 0 product guide PG060","year":"2014","key":"ref20"},{"journal-title":"Max 10 FPGA Device Architecture","year":"2017","key":"ref22"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1007\/978-981-13-0824-6"},{"key":"ref24","first-page":"498","article-title":"The control technology of integrity and legitimacy of LUT-oriented information object usage by self-recovering digital watermark","volume":"1356","author":"zashcholkin","year":"0","journal-title":"CEUR Workshop Proceedings"},{"journal-title":"Truncated binary multipliers with minimum mean square error Analytical characterization circuit implementation and applications","year":"2008","author":"garofalo","key":"ref41"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2015.2392104"},{"journal-title":"High-Performance Computing Using FPGAs","year":"2016","author":"vanderbauwhede","key":"ref26"},{"key":"ref25","first-page":"1014","article-title":"The implementation of extended arithmetic's on FPGA-based structures","author":"palagin","year":"2017","journal-title":"Proc of the 9th IEEE International Conference on Intelligent Data Acquisition and Advanced Computing Systems Technology and Applications"}],"event":{"name":"2019 10th IEEE International Conference on Intelligent Data Acquisition and Advanced Computing Systems: Technology and Applications (IDAACS)","start":{"date-parts":[[2019,9,18]]},"location":"Metz, France","end":{"date-parts":[[2019,9,21]]}},"container-title":["2019 10th IEEE International Conference on Intelligent Data Acquisition and Advanced Computing Systems: Technology and Applications (IDAACS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8908800\/8924230\/08924435.pdf?arnumber=8924435","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,17]],"date-time":"2022-07-17T21:46:54Z","timestamp":1658094414000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8924435\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,9]]},"references-count":41,"URL":"https:\/\/doi.org\/10.1109\/idaacs.2019.8924435","relation":{},"subject":[],"published":{"date-parts":[[2019,9]]}}}