{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,12,18]],"date-time":"2025-12-18T14:17:58Z","timestamp":1766067478008,"version":"3.28.0"},"reference-count":20,"publisher":"IEEE","license":[{"start":{"date-parts":[[2021,9,22]],"date-time":"2021-09-22T00:00:00Z","timestamp":1632268800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2021,9,22]],"date-time":"2021-09-22T00:00:00Z","timestamp":1632268800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2021,9,22]],"date-time":"2021-09-22T00:00:00Z","timestamp":1632268800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2021,9,22]]},"DOI":"10.1109\/idaacs53288.2021.9660906","type":"proceedings-article","created":{"date-parts":[[2022,1,5]],"date-time":"2022-01-05T20:43:03Z","timestamp":1641415383000},"page":"1141-1146","source":"Crossref","is-referenced-by-count":1,"title":["Formal Methods of FPGA Project Verification Flow"],"prefix":"10.1109","author":[{"given":"Serhii","family":"Naumenko","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Viktoriia","family":"Moskalets","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Oleg","family":"Odarushchenko","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Elena","family":"Odarushchenko","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Volodymyr","family":"Peschanenko","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Larysa","family":"Degtyareva","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Oleksandr","family":"Letychevskyi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1007\/978-90-481-9157-4"},{"key":"ref11","first-page":"52","article-title":"Metodology of NPP I&C system algorithms and software verification expert analysis","author":"kharchenko","year":"2001","journal-title":"Proceedings of Workshop on Licensing and Operating Experience of Computer-Based I&C Systems"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/IEEESTD.2017.8055462"},{"year":"0","key":"ref13"},{"journal-title":"ITU Recommendation Z 120 Message Sequence Charts (MSC)","year":"0","key":"ref14"},{"journal-title":"Vc formal","year":"0","key":"ref15"},{"journal-title":"Vivado Verification","year":"0","key":"ref16"},{"journal-title":"Finding race conditions in real-time code byusing formal software verification","year":"2014","author":"ehlers","key":"ref17"},{"journal-title":"JasPer","year":"0","key":"ref18"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1007\/s10559-020-00289-8"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/1234741.1234767"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TIE.2010.2050291"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/32.888629"},{"key":"ref5","first-page":"188","author":"bakhmach","year":"2008","journal-title":"FPGA-based NPP Instrumentation and Control Systems Development and Safety Assessment"},{"journal-title":"Quantifying FPGA Verification Effectiveness","year":"2020","author":"foster","key":"ref8"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1115\/ICONE26-82270"},{"journal-title":"Functional Safety – An IEC 61508 SIL 3 Compliant Development Process","year":"0","author":"medoff","key":"ref2"},{"key":"ref1","first-page":"148","article-title":"Certification of FPGA-based safety instrumentation and control platform in accordance with IEC 61508","volume":"1","author":"andrashov","year":"2011","journal-title":"Proceeding of the 1st International Workshop Critical Infrastructure Safety and Security CrISS-DESSERT"},{"key":"ref9","first-page":"6.1","article-title":"Dezign Optimization for Altera Devices","volume":"2","year":"2004","journal-title":"Qii520072 0 Quartus II Handbook"},{"journal-title":"Radiy","year":"0","key":"ref20"}],"event":{"name":"2021 11th IEEE International Conference on Intelligent Data Acquisition and Advanced Computing Systems: Technology and Applications (IDAACS)","start":{"date-parts":[[2021,9,22]]},"location":"Cracow, Poland","end":{"date-parts":[[2021,9,25]]}},"container-title":["2021 11th IEEE International Conference on Intelligent Data Acquisition and Advanced Computing Systems: Technology and Applications (IDAACS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9660827\/9660386\/09660906.pdf?arnumber=9660906","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,5,10]],"date-time":"2022-05-10T16:56:44Z","timestamp":1652201804000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9660906\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,9,22]]},"references-count":20,"URL":"https:\/\/doi.org\/10.1109\/idaacs53288.2021.9660906","relation":{},"subject":[],"published":{"date-parts":[[2021,9,22]]}}}