{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,7,20]],"date-time":"2025-07-20T03:29:31Z","timestamp":1752982171408,"version":"3.28.0"},"reference-count":20,"publisher":"IEEE","license":[{"start":{"date-parts":[[2023,9,7]],"date-time":"2023-09-07T00:00:00Z","timestamp":1694044800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2023,9,7]],"date-time":"2023-09-07T00:00:00Z","timestamp":1694044800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2023,9,7]]},"DOI":"10.1109\/idaacs58523.2023.10348654","type":"proceedings-article","created":{"date-parts":[[2023,12,21]],"date-time":"2023-12-21T19:20:33Z","timestamp":1703186433000},"page":"590-595","source":"Crossref","is-referenced-by-count":5,"title":["FPGA-based Accelerator for FFT-Processing in Edge Computing"],"prefix":"10.1109","author":[{"given":"Peter","family":"Schulz","sequence":"first","affiliation":[{"name":"HAW Hamburg,Hamburg,D-20099"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Grigore","family":"Sleahtitchi","sequence":"additional","affiliation":[{"name":"HAW Hamburg,Hamburg,D-20099"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref1","article-title":"Antrag auf Gewahrung einer Zuwendung im Rahmen der Forderma\u00dfnahme Call for Transfer","author":"Schulz","year":"2020","journal-title":"internal document, unpublished"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/VCIP.2017.8305121"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/3132211.3134460"},{"key":"ref4","article-title":"Advancing the use of FPGA co-processors through platforms and high-level design flow","author":"Hill","year":"2011","journal-title":"White Paper, Xilinx WP394"},{"key":"ref5","article-title":"Partial reconfiguration of a hardware accelerator with vivado design suite for Zynq-7000 AP SoC processor","author":"Kohn","year":"2015","journal-title":"Application Note, XAPPI231"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2019.2943179"},{"article-title":"The fast Fourier transform in hardware: A tutorial based on an FPGA implementation","volume-title":"published on ResearchGate","author":"Slade","key":"ref7"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/1723112.1723122"},{"key":"ref9","article-title":"FPGA on the Edge","author":"Sleahtitchi","year":"2021","journal-title":"internal project reports"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2016.2603219"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.23919\/date56975.2023.10137021"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/lamc50424.2021.9602484"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/acssc.2015.7421167"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/atsip.2018.8364454"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/tvlsi.2016.2567784"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/icdcsyst.2014.6926131"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/vlsid.2013.169"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/icsima.2018.8688777"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/prime58259.2023.10161859"},{"issue":"DS890","key":"ref20","article-title":"UltraScale Architecture and Product Data Sheet: Overview","volume":"4.4","year":"2023","journal-title":"AMD\/Xilinx product specification document"}],"event":{"name":"2023 IEEE 12th International Conference on Intelligent Data Acquisition and Advanced Computing Systems: Technology and Applications (IDAACS)","start":{"date-parts":[[2023,9,7]]},"location":"Dortmund, Germany","end":{"date-parts":[[2023,9,9]]}},"container-title":["2023 IEEE 12th International Conference on Intelligent Data Acquisition and Advanced Computing Systems: Technology and Applications (IDAACS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/10348627\/10348628\/10348654.pdf?arnumber=10348654","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,1,12]],"date-time":"2024-01-12T03:16:53Z","timestamp":1705029413000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10348654\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,9,7]]},"references-count":20,"URL":"https:\/\/doi.org\/10.1109\/idaacs58523.2023.10348654","relation":{},"subject":[],"published":{"date-parts":[[2023,9,7]]}}}