{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,4]],"date-time":"2024-09-04T14:37:27Z","timestamp":1725460647834},"reference-count":13,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2013,12]]},"DOI":"10.1109\/idt.2013.6727074","type":"proceedings-article","created":{"date-parts":[[2014,1,31]],"date-time":"2014-01-31T18:35:43Z","timestamp":1391193343000},"page":"1-6","source":"Crossref","is-referenced-by-count":0,"title":["Functional verification of complete sequential behaviors: A formal treatment of discrepancies between system-level and RTL descriptions"],"prefix":"10.1109","author":[{"given":"Carlos Ivan","family":"Castro Marquez","sequence":"first","affiliation":[]},{"given":"Marius","family":"Strum","sequence":"additional","affiliation":[]},{"given":"Wang Jiang","family":"Chau","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"13","doi-asserted-by":"publisher","DOI":"10.1007\/b105236"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2011.5722241"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/LATW.2013.6562666"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2012.6176449"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1007\/s10836-013-5372-1"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/MEMCOD.2007.371236"},{"key":"1","first-page":"154","article-title":"Hardware model checking:Status, challenges, and opportunities","author":"talupur","year":"2011","journal-title":"Formal Methods in Computer-Aided Design (FMCAD)"},{"year":"0","key":"7"},{"journal-title":"Equivalence Checking of Digital Circuits Fundamentals Principles Methods","year":"2004","author":"molitor","key":"6"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/ASE.2011.6100143"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/HLDVT.2010.5496658"},{"key":"9","first-page":"1500","article-title":"Optimizing equivalence checking for behavioral synthesis","author":"hao","year":"2010","journal-title":"Design Automation and Test in Europe"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2009.5090657"}],"event":{"name":"2013 Design and Test Symposium (IDT)","start":{"date-parts":[[2013,12,16]]},"location":"Marrakesh, Morocco","end":{"date-parts":[[2013,12,18]]}},"container-title":["2013 8th IEEE Design and Test Symposium"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6717187\/6727071\/06727074.pdf?arnumber=6727074","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,22]],"date-time":"2017-03-22T18:39:43Z","timestamp":1490207983000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6727074\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,12]]},"references-count":13,"URL":"https:\/\/doi.org\/10.1109\/idt.2013.6727074","relation":{},"subject":[],"published":{"date-parts":[[2013,12]]}}}