{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,8]],"date-time":"2024-09-08T02:02:07Z","timestamp":1725760927204},"reference-count":15,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2013,12]]},"DOI":"10.1109\/idt.2013.6727097","type":"proceedings-article","created":{"date-parts":[[2014,1,31]],"date-time":"2014-01-31T23:35:43Z","timestamp":1391211343000},"page":"1-5","source":"Crossref","is-referenced-by-count":2,"title":["Single-ended sense amplifier robustness evaluation for OxRRAM technology"],"prefix":"10.1109","author":[{"given":"H.","family":"Aziza","sequence":"first","affiliation":[]},{"given":"M.","family":"Bocquet","sequence":"additional","affiliation":[]},{"given":"M.","family":"Moreau","sequence":"additional","affiliation":[]},{"given":"J-M.","family":"Portal","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"15","first-page":"20","article-title":"Peripheral circuitry impact on eeprom threshold voltage","author":"aziza","year":"2007","journal-title":"Proceedings of Non-Volatile Memory Technology Symposium (NVMTS)"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/ISDRS.2011.6135356"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1049\/el.2010.1894"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/MTDT.2002.1029774"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1016\/j.jnoncrysol.2010.11.010"},{"key":"3","doi-asserted-by":"crossref","first-page":"85","DOI":"10.1145\/2765491.2765508","article-title":"Crossbar architecture based on 2R complementary resistive switching memory cell","author":"zhao","year":"2012","journal-title":"2012 IEEE\/ACM International Symposium on Nanoscale Architectures (NANOARCH) NANOARCH"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/ESSDERC.2010.5618197"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1016\/0038-1101(64)90131-5"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/DTIS.2006.1708695"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/IDT.2011.6123106"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/IRPS.2011.5784590"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/NVMTS.2011.6137089"},{"key":"4","first-page":"85","article-title":"Synchronous non-volatile logic gate design based on resistive switching memories","author":"zaho","year":"2013","journal-title":"Circuits and Systems I IEEE Transactions on"},{"key":"9","first-page":"3","article-title":"Investigation of the impact of the oxide thickness and rESET conditions on disturb in hfO2-RRAM integrated in a 65nm cMOS technology","author":"diokh","year":"2013","journal-title":"International Reliability Physics Symposium"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/FTFC.2013.6577779"}],"event":{"name":"2013 Design and Test Symposium (IDT)","start":{"date-parts":[[2013,12,16]]},"location":"Marrakesh, Morocco","end":{"date-parts":[[2013,12,18]]}},"container-title":["2013 8th IEEE Design and Test Symposium"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6717187\/6727071\/06727097.pdf?arnumber=6727097","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,3,24]],"date-time":"2022-03-24T23:30:54Z","timestamp":1648164654000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6727097\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,12]]},"references-count":15,"URL":"https:\/\/doi.org\/10.1109\/idt.2013.6727097","relation":{},"subject":[],"published":{"date-parts":[[2013,12]]}}}