{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,29]],"date-time":"2025-09-29T11:51:21Z","timestamp":1759146681589},"reference-count":21,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2013,12]]},"DOI":"10.1109\/idt.2013.6727103","type":"proceedings-article","created":{"date-parts":[[2014,1,31]],"date-time":"2014-01-31T23:35:43Z","timestamp":1391211343000},"page":"1-6","source":"Crossref","is-referenced-by-count":2,"title":["Reducing random-dopant fluctuation impact on core-speed and power variability in many-core platforms"],"prefix":"10.1109","author":[{"given":"Sohaib","family":"Majzoub","sequence":"first","affiliation":[]},{"given":"Zaid","family":"Alars","sequence":"additional","affiliation":[]},{"given":"Said","family":"Hamdioui","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"doi-asserted-by":"publisher","key":"19","DOI":"10.1109\/TVLSI.2006.876103"},{"doi-asserted-by":"publisher","key":"17","DOI":"10.1109\/NOCS.2008.4492731"},{"doi-asserted-by":"publisher","key":"18","DOI":"10.1093\/ietele\/e88-c.4.509"},{"doi-asserted-by":"publisher","key":"15","DOI":"10.1145\/775832.775920"},{"doi-asserted-by":"publisher","key":"16","DOI":"10.1109\/MDT.2006.156"},{"key":"13","first-page":"680","author":"taur","year":"2009","journal-title":"Fundamentals of Modern VLSI Devices"},{"doi-asserted-by":"publisher","key":"14","DOI":"10.1145\/1283780.1283792"},{"year":"2003","author":"hodges","journal-title":"Analysis and Design of Digital Integrated Circuits","key":"11"},{"doi-asserted-by":"publisher","key":"12","DOI":"10.1109\/ISQED.2009.4810397"},{"doi-asserted-by":"publisher","key":"3","DOI":"10.1145\/1146909.1147109"},{"key":"21","doi-asserted-by":"crossref","first-page":"201","DOI":"10.1145\/1594233.1594283","article-title":"Optimizing total power of manycore processors considering voltage scaling limit and process variations","author":"lee","year":"2009","journal-title":"International Symposium on Low Power Electronics and Design"},{"doi-asserted-by":"publisher","key":"2","DOI":"10.1109\/ISQED.2008.4479828"},{"doi-asserted-by":"publisher","key":"20","DOI":"10.1109\/TCAD.2010.2043587"},{"key":"1","doi-asserted-by":"crossref","first-page":"817","DOI":"10.1145\/1278480.1278684","article-title":"A General Framework for Spatial Correlation Modeling in VLSI Design","author":"liu","year":"2007","journal-title":"2007 44th ACM\/IEEE Design Automation Conference DAC"},{"doi-asserted-by":"publisher","key":"10","DOI":"10.1109\/DATE.2007.364539"},{"doi-asserted-by":"publisher","key":"7","DOI":"10.1109\/LPE.2005.195478"},{"doi-asserted-by":"publisher","key":"6","DOI":"10.1109\/TSM.2007.913186"},{"doi-asserted-by":"publisher","key":"5","DOI":"10.1109\/TCAD.2008.927672"},{"doi-asserted-by":"publisher","key":"4","DOI":"10.1109\/ASPDAC.2008.4484007"},{"doi-asserted-by":"publisher","key":"9","DOI":"10.1109\/ICCD.2007.4601891"},{"key":"8","first-page":"221","author":"pierret","year":"2002","journal-title":"Advanced Semiconductor Fundamentals"}],"event":{"name":"2013 Design and Test Symposium (IDT)","start":{"date-parts":[[2013,12,16]]},"location":"Marrakesh, Morocco","end":{"date-parts":[[2013,12,18]]}},"container-title":["2013 8th IEEE Design and Test Symposium"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6717187\/6727071\/06727103.pdf?arnumber=6727103","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,7,10]],"date-time":"2023-07-10T05:29:46Z","timestamp":1688966986000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6727103\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,12]]},"references-count":21,"URL":"https:\/\/doi.org\/10.1109\/idt.2013.6727103","relation":{},"subject":[],"published":{"date-parts":[[2013,12]]}}}