{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,5]],"date-time":"2024-09-05T11:45:59Z","timestamp":1725536759545},"reference-count":20,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2014,12]]},"DOI":"10.1109\/idt.2014.7038597","type":"proceedings-article","created":{"date-parts":[[2015,2,17]],"date-time":"2015-02-17T15:01:34Z","timestamp":1424185294000},"page":"112-117","source":"Crossref","is-referenced-by-count":0,"title":["Impact analysis of resistive bridge within deep submicron Secured CMOS circuits"],"prefix":"10.1109","author":[{"given":"G. Ait","family":"Abdelmalek","sequence":"first","affiliation":[]},{"given":"R.","family":"Ziani","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"19","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1992.527915"},{"journal-title":"Essentials of Electronic Testing for Digital Memory and Mixed-Signal VLSI Circuits","year":"2000","author":"bushnell","key":"17"},{"journal-title":"Mod\ufffdlisation de d\ufffd Fauts Param\ufffdtriques en Vue de Tests Statiques et Dynamiquesth\ufffdse de Doctorat","year":"2009","author":"houarche","key":"18"},{"key":"15","first-page":"172","article-title":"Masked dual-rail pre-charge logic: Dparesistance without routing constraints","author":"popp","year":"2005","journal-title":"CHES"},{"key":"16","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2010.5456932"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2004.1268856"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1109\/VLSISOC.2007.4402510"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1049\/ip-e.1993.0011"},{"key":"12","first-page":"403","article-title":"A dynamic and differential CMOS logic with signal independent power consumption to withstand differential power analysis on smart cards","author":"tiri","year":"2002","journal-title":"Proceedings of the 28th European Solid-State Circuits Conference ESSCIRC"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/VTEST.1995.512635"},{"key":"20","first-page":"544","article-title":"Electrical characte ristics and testing considerations for gate oxide shorts in cmos ic's","author":"hawkins","year":"1985","journal-title":"Proc Int Test Conf"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/VTEST.1994.292283"},{"key":"1","first-page":"292","article-title":"Resistive shorts within cmos gates","author":"hao","year":"1991","journal-title":"International Test Conference"},{"journal-title":"Testing Delay-Insensitive Circuits","year":"1996","author":"hazewindus","key":"10"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.1993.394020"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2000.894196"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.1997.643976"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/ETS.2008.19"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1016\/0167-9260(95)00012-5"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2001.968700"}],"event":{"name":"2014 9th International Design & Test Symposium (IDT)","start":{"date-parts":[[2014,12,16]]},"location":"Algeries, Algeria","end":{"date-parts":[[2014,12,18]]}},"container-title":["2014 9th International Design and Test Symposium (IDT)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7021862\/7038563\/07038597.pdf?arnumber=7038597","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,23]],"date-time":"2017-03-23T22:22:57Z","timestamp":1490307777000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7038597\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,12]]},"references-count":20,"URL":"https:\/\/doi.org\/10.1109\/idt.2014.7038597","relation":{},"subject":[],"published":{"date-parts":[[2014,12]]}}}