{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,22]],"date-time":"2024-10-22T15:04:23Z","timestamp":1729609463103,"version":"3.28.0"},"reference-count":18,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2014,12]]},"DOI":"10.1109\/idt.2014.7038599","type":"proceedings-article","created":{"date-parts":[[2015,2,17]],"date-time":"2015-02-17T15:01:34Z","timestamp":1424185294000},"page":"124-129","source":"Crossref","is-referenced-by-count":0,"title":["Computational complexity in test-generation algorithms"],"prefix":"10.1109","author":[{"given":"Jozsef","family":"Sziray","sequence":"first","affiliation":[]}],"member":"263","reference":[{"key":"17","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2009.177"},{"key":"18","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2009.178"},{"key":"15","doi-asserted-by":"publisher","DOI":"10.1007\/978-90-481-2360-5"},{"key":"16","doi-asserted-by":"publisher","DOI":"10.1109\/MTV.2009.24"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1981.1675757"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1983.1676174"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1976.1674663"},{"key":"12","doi-asserted-by":"crossref","first-page":"20","DOI":"10.1109\/MTV.2006.21","article-title":"Test calculation for logic and delay faults in digital circuits","author":"sziray","year":"2006","journal-title":"IEEE Microprocessor Test and Verification Workshop (MTV-06) Proceedings"},{"journal-title":"Introduction to Algorithms","year":"2001","author":"cormen","key":"3"},{"journal-title":"Introduction to Automata Theory Languages and Computation","year":"2001","author":"hopcroft","key":"2"},{"journal-title":"Elements of the Theory of Computation","year":"1998","author":"lewis","key":"1"},{"key":"10","first-page":"223","article-title":"Functional level test calculation and fault simulation for logic networks","author":"sziray","year":"1982","journal-title":"Discrete Simulation and Related Fields"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/9780470544389"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1147\/rd.104.0278"},{"key":"5","doi-asserted-by":"crossref","DOI":"10.7551\/mitpress\/4317.001.0001","author":"fujiwara","year":"1985","journal-title":"Logic Testing and Design for Testability"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/T-C.1975.224205"},{"key":"9","first-page":"251","article-title":"A comprehensive method for the test calculation of complex digital circuits","volume":"41","author":"sziray","year":"1998","journal-title":"Periodica Polytechnica Budapest Techn Univ Series of Electronic Eng"},{"key":"8","first-page":"3","article-title":"Test calculation for logic networks by composite justification","volume":"5","author":"sziray","year":"1979","journal-title":"Digital Processes"}],"event":{"name":"2014 9th International Design & Test Symposium (IDT)","start":{"date-parts":[[2014,12,16]]},"location":"Algeries, Algeria","end":{"date-parts":[[2014,12,18]]}},"container-title":["2014 9th International Design and Test Symposium (IDT)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7021862\/7038563\/07038599.pdf?arnumber=7038599","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,8,20]],"date-time":"2019-08-20T21:04:17Z","timestamp":1566335057000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7038599\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,12]]},"references-count":18,"URL":"https:\/\/doi.org\/10.1109\/idt.2014.7038599","relation":{},"subject":[],"published":{"date-parts":[[2014,12]]}}}