{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,7]],"date-time":"2024-09-07T09:22:25Z","timestamp":1725700945639},"reference-count":22,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2015,12]]},"DOI":"10.1109\/idt.2015.7396737","type":"proceedings-article","created":{"date-parts":[[2016,2,4]],"date-time":"2016-02-04T16:56:52Z","timestamp":1454605012000},"page":"60-65","source":"Crossref","is-referenced-by-count":2,"title":["Guiding intelligent testbench automation using data mining and formal methods"],"prefix":"10.1109","author":[{"given":"Eman El","family":"Mandouh","sequence":"first","affiliation":[]},{"given":"Amr G.","family":"Wassal","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/HLDVT.2006.320005"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/1029894.1029901"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/1065579.1065786"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2010.5457129"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2010.5419813"},{"key":"ref15","first-page":"2317","article-title":"Automatic Generation of Hardware Design Properties from Simulation Traces","author":"el-mandouh","year":"2010","journal-title":"IEEE Intemational Symposium on Circuits and Systems (ISCAS)"},{"year":"2014","key":"ref16","article-title":"Test Specification Language - the past, present and the future"},{"year":"2014","key":"ref17","article-title":"Mentor Graphics Proposes New Accellera Standards Committee for Graph-Based Test Specification Standard"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/775047.775109"},{"key":"ref19","article-title":"Efficient Implemantation of Apriori and Eclat","author":"borgelt","year":"2003","journal-title":"In FIMI Proceedings of the IEEE ICDM Workshop on Frequent Item Set Mining"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1007\/BFb0031805"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.1999.781305"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2005.162"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2000.835151"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.884494"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.2003.1219010"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/2071356.2071363"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2006.183"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1007\/s10710-005-2985-x"},{"journal-title":"Inc Unified Coverage Interoperability Standard (UCIS) Accellera Organization Inc","article-title":"Accellera Organization","year":"2012","key":"ref20"},{"year":"0","key":"ref22","article-title":"Opencores benchmarks"},{"journal-title":"IEEE 1800-2012 System Verilog Unified Hardware Design","article-title":"Specification and Verification Language","year":"0","key":"ref21"}],"event":{"name":"2015 10th International Design & Test Symposium (IDT)","start":{"date-parts":[[2015,12,14]]},"location":"Dead Sea, Amman, Jordan","end":{"date-parts":[[2015,12,16]]}},"container-title":["2015 10th International Design & Test Symposium (IDT)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7383418\/7396715\/07396737.pdf?arnumber=7396737","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,21]],"date-time":"2017-03-21T08:49:22Z","timestamp":1490086162000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7396737\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,12]]},"references-count":22,"URL":"https:\/\/doi.org\/10.1109\/idt.2015.7396737","relation":{},"subject":[],"published":{"date-parts":[[2015,12]]}}}