{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,30]],"date-time":"2024-10-30T04:08:58Z","timestamp":1730261338628,"version":"3.28.0"},"reference-count":12,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2015,12]]},"DOI":"10.1109\/idt.2015.7396747","type":"proceedings-article","created":{"date-parts":[[2016,2,4]],"date-time":"2016-02-04T21:56:52Z","timestamp":1454623012000},"page":"118-123","source":"Crossref","is-referenced-by-count":0,"title":["A method of LFSR seed generation for hierarchical BIST"],"prefix":"10.1109","author":[{"given":"Kosuke","family":"Sawaki","sequence":"first","affiliation":[]},{"given":"Satoshi","family":"Ohtake","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","first-page":"42","article-title":"Hierarchical BIST: Test-per-clock BIST with low overhead","author":"yamaguchi","year":"2002","journal-title":"Digest of Papers of Workshop on RTL and High Level Testing (WRTLT)"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2001.990302"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2000.835171"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/LATW.2015.7102512"},{"key":"ref11","article-title":"Efficient shift registers, LFSR counters, and long pseudorandom sequence generators","volume":"xapp 52","author":"alfke","year":"1996","journal-title":"Xilinx Application Note"},{"key":"ref5","first-page":"237","article-title":"LFSR-coded test patterns for scan designs","author":"konemann","year":"1991","journal-title":"Proc of European Test Conference"},{"key":"ref12","first-page":"1047","article-title":"Automated synthesis of phase shifters for buil-in self-test applications","author":"rajski","year":"1998","journal-title":"Proc of International Test Conference"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1996.557123"},{"key":"ref7","article-title":"A method of LFSR seed generation for delay fault BIST using constrained ATPG","author":"honda","year":"2014","journal-title":"Digest of Papers of Workshop on RTL and High Level Testing (WRTLT)"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2000.893627"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/43.55189"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/VTEST.1996.510838"}],"event":{"name":"2015 10th International Design & Test Symposium (IDT)","start":{"date-parts":[[2015,12,14]]},"location":"Dead Sea, Amman, Jordan","end":{"date-parts":[[2015,12,16]]}},"container-title":["2015 10th International Design & Test Symposium (IDT)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7383418\/7396715\/07396747.pdf?arnumber=7396747","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,21]],"date-time":"2017-03-21T12:46:06Z","timestamp":1490100366000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7396747\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,12]]},"references-count":12,"URL":"https:\/\/doi.org\/10.1109\/idt.2015.7396747","relation":{},"subject":[],"published":{"date-parts":[[2015,12]]}}}