{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,11]],"date-time":"2025-09-11T17:59:22Z","timestamp":1757613562430,"version":"3.44.0"},"reference-count":22,"publisher":"IEEE","license":[{"start":{"date-parts":[[2016,12,1]],"date-time":"2016-12-01T00:00:00Z","timestamp":1480550400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2016,12,1]],"date-time":"2016-12-01T00:00:00Z","timestamp":1480550400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2016,12]]},"DOI":"10.1109\/idt.2016.7843010","type":"proceedings-article","created":{"date-parts":[[2017,2,7]],"date-time":"2017-02-07T15:56:19Z","timestamp":1486482979000},"page":"31-36","source":"Crossref","is-referenced-by-count":0,"title":["Design of advanced 2D and 3D FPGAs: Architecture-level exploration and algorithm-level optimization"],"prefix":"10.1109","author":[{"given":"Sonda","family":"Chtourou","sequence":"first","affiliation":[{"name":"CES Research Laboratory, University of Sfax, Tunisia"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Mohamed","family":"Abid","sequence":"additional","affiliation":[{"name":"CES Research Laboratory, University of Sfax, Tunisia"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Zied","family":"Marrakchi","sequence":"additional","affiliation":[{"name":"Mentor Graphics, Tunis, Tunisia"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Emna","family":"Amouri","sequence":"additional","affiliation":[{"name":"LIP6 Research Laboratory, UPMC, Paris, France"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Habib","family":"Mehrez","sequence":"additional","affiliation":[{"name":"LIP6 Research Laboratory, UPMC, Paris, France"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1126\/science.220.4598.671"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/201310.201328"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1016\/j.micpro.2015.11.011"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2004.824300"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1155\/2009\/259837"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2004.1393249"},{"key":"ref16","first-page":"3","article-title":"Exploration and optimization of a homogeneous Mesh of Clusters-based FPGA Architectures, Journal of Microelectronics","volume":"46","author":"chtourou","year":"2016","journal-title":"Electronic Components and Materials"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2002.996687"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/PDP.2016.77"},{"key":"ref19","article-title":"Logic Synthesis and optimization benchmarks","author":"yang","year":"1991","journal-title":"Version 3 0 Microelectronics Center of North Carolina (MCNC)"},{"key":"ref4","first-page":"275","volume":"4","author":"siozios","year":"2008","journal-title":"A Power-Aware Placement and Routing Algorithm Targeting 3D FPGAs"},{"key":"ref3","article-title":"Architecture and CAD for Deep Sub-micron FPGAs","author":"betz","year":"1999","journal-title":"The Springer International Series in Engineering and Computer Science"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2014.2359385"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2012.6412139"},{"journal-title":"ABC","year":"2012","author":"mishchenko","key":"ref8"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2010.31"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/871506.871541"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.884574"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/296399.296426"},{"journal-title":"IWLS Benchmarks","year":"2005","key":"ref20"},{"key":"ref22","first-page":"285","article-title":"Multilevel k-way Hypergraph Partitioning","volume":"11","author":"karypis","year":"1999","journal-title":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems"},{"key":"ref21","first-page":"1","article-title":"Designing a 3D Tree-based FPGA, Optimization of Butter programmable interconnect topology using 3D Technology","author":"pangracious","year":"2013","journal-title":"3D Systems Integration Conference (3DIC)"}],"event":{"name":"2016 11th International Design & Test Symposium (IDT)","start":{"date-parts":[[2016,12,18]]},"location":"Hammamet, Tunisia","end":{"date-parts":[[2016,12,20]]}},"container-title":["2016 11th International Design & Test Symposium (IDT)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7833312\/7842992\/07843010.pdf?arnumber=7843010","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,9,4]],"date-time":"2025-09-04T21:59:05Z","timestamp":1757023145000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/7843010\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,12]]},"references-count":22,"URL":"https:\/\/doi.org\/10.1109\/idt.2016.7843010","relation":{},"subject":[],"published":{"date-parts":[[2016,12]]}}}