{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,9,30]],"date-time":"2026-09-30T15:21:07Z","timestamp":1790781667231,"version":"4.1.0"},"reference-count":25,"publisher":"IEEE","license":[{"start":{"date-parts":[[2016,12,1]],"date-time":"2016-12-01T00:00:00Z","timestamp":1480550400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2016,12,1]],"date-time":"2016-12-01T00:00:00Z","timestamp":1480550400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2016,12]]},"DOI":"10.1109\/idt.2016.7843032","type":"proceedings-article","created":{"date-parts":[[2017,2,7]],"date-time":"2017-02-07T15:56:19Z","timestamp":1486482979000},"page":"154-159","source":"Crossref","is-referenced-by-count":14,"title":["A comparison and performance evaluation of FPGA soft-cores for embedded multi-core systems"],"prefix":"10.1109","author":[{"given":"Mariem","family":"Makni","sequence":"first","affiliation":[{"name":"LAMIH, University of Valenciennes, France"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Mouna","family":"Baklouti","sequence":"additional","affiliation":[{"name":"National Engineering School of Sfax, Tunisia"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Smail","family":"Niar","sequence":"additional","affiliation":[{"name":"LAMIH, University of Valenciennes, France"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Mohamed Wassim","family":"Jmal","sequence":"additional","affiliation":[{"name":"National Engineering School of Sfax, Tunisia"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Mohamed","family":"Abid","sequence":"additional","affiliation":[{"name":"National Engineering School of Sfax, Tunisia"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref10","year":"2008","journal-title":"LEON3 Processor Users Manual XT Edition Gaisler Research"},{"key":"ref11","year":"0","journal-title":"Aeroflex Gaisler AB GR712RC Dual-Core LEON3FT SPARC V8 Processor"},{"key":"ref12","year":"0","journal-title":"Freescale"},{"key":"ref13","author":"kranenburg","year":"2010","journal-title":"MB-LITE A robust lightweight soft-core implementation of the MicroBlaze architecture"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1007\/s11265-007-0153-7"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2005.239"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2010.38"},{"key":"ref17","year":"0","journal-title":"Picoblaze"},{"key":"ref18","year":"0","journal-title":"OpenFire"},{"key":"ref19","author":"lampret","year":"2001","journal-title":"OpenRISC1200 IP Core Specification"},{"key":"ref4","year":"0","journal-title":"Xilinx (2015) Zynq-7000 All Programmable SoC"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.887921"},{"key":"ref6","year":"2012","journal-title":"Xilinx Inc"},{"key":"ref5","year":"2012","journal-title":"Altera Corp"},{"key":"ref8","year":"2006","journal-title":"Gaisler Research Website"},{"key":"ref7","year":"2006","journal-title":"Opencores org Website"},{"key":"ref2","article-title":"A design and an implementation of a parallel based SIMD architecture for SoC on FPGA","author":"baklouti","year":"2008","journal-title":"Proc DASIP"},{"key":"ref9","year":"2012","journal-title":"Xilinx MicroBlaze Processor Reference Guide-Embedded Development Kit EDK 13 2"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2003.1213480"},{"key":"ref20","year":"0","journal-title":"MB-Lite"},{"key":"ref22","year":"2002","journal-title":"Evaluating DSP Processors Performance"},{"key":"ref21","year":"0","journal-title":"aeMB"},{"key":"ref24","author":"lizy","year":"0","journal-title":"Performance evaluation Techniques tools and benchmarks Electrical and computer engineering department"},{"key":"ref23","author":"stolze","year":"0"},{"key":"ref25","article-title":"Performance Evaluation of FPGA Soft Cores Configurations Case of Xilinx MicroBlaze","author":"mhadhbi","year":"2014","journal-title":"International Journal of Computer Science Communication & Information Technology"}],"event":{"name":"2016 11th International Design & Test Symposium (IDT)","location":"Hammamet, Tunisia","start":{"date-parts":[[2016,12,18]]},"end":{"date-parts":[[2016,12,20]]}},"container-title":["2016 11th International Design & Test Symposium (IDT)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7833312\/7842992\/07843032.pdf?arnumber=7843032","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,9,4]],"date-time":"2025-09-04T21:58:55Z","timestamp":1757023135000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/7843032\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,12]]},"references-count":25,"URL":"https:\/\/doi.org\/10.1109\/idt.2016.7843032","relation":{},"subject":[],"published":{"date-parts":[[2016,12]]}}}