{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,12]],"date-time":"2026-03-12T13:58:37Z","timestamp":1773323917633,"version":"3.50.1"},"reference-count":24,"publisher":"IEEE","license":[{"start":{"date-parts":[[2008,10,1]],"date-time":"2008-10-01T00:00:00Z","timestamp":1222819200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2008,10,1]],"date-time":"2008-10-01T00:00:00Z","timestamp":1222819200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2008,10]]},"DOI":"10.1109\/iiswc.2008.4636101","type":"proceedings-article","created":{"date-parts":[[2008,9,30]],"date-time":"2008-09-30T11:27:01Z","timestamp":1222774021000},"page":"163-172","source":"Crossref","is-referenced-by-count":17,"title":["Accelerating multi-core processor design space evaluation using automatic multi-threaded workload synthesis"],"prefix":"10.1109","author":[{"given":"Clay","family":"Hughes","sequence":"first","affiliation":[{"name":"Intelligent Design of Efficient Architecture Lab(IDEAL), Department of Electrical and Computer Engineering, University of Florida, USA"}]},{"family":"Tao Li","sequence":"additional","affiliation":[{"name":"Intelligent Design of Efficient Architecture Lab(IDEAL), Department of Electrical and Computer Engineering, University of Florida, USA"}]}],"member":"263","reference":[{"key":"19","author":"genbrugge","year":"2007","journal-title":"Statistical Simulation of Chip Multiprocessors Running Multi-Program Workloads ICCD"},{"key":"22","author":"woo","year":"1995","journal-title":"Characterization and Methodological Considerations"},{"key":"17","author":"eeckhout","year":"2001","journal-title":"Hybrid Analytical-Statistical Modeling for Efficiently Exploring Architecture and Workload Design Spaces PACT"},{"key":"23","year":"0","journal-title":"VTune"},{"key":"18","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2003.1240210"},{"key":"24","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.36"},{"key":"15","author":"biesbrouck","year":"2006","journal-title":"Considering All Starting Points for Simultaneous Multi-threading Simulation ISPASS"},{"key":"16","author":"nussbaum","year":"2001","journal-title":"Modeling Superscalar Processors via Statistical Simulation PACT"},{"key":"13","author":"sherwood","year":"2002","journal-title":"Automatically Characterizing Large Scale Program Behavior ASPLOS"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1145\/859626.859629"},{"key":"11","year":"0"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1137\/1.9781611970104"},{"key":"21","first-page":"71","article-title":"HLS: combining statistical and symbolic simulation to guide microprocessor designs","author":"oskin","year":"2000","journal-title":"Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat No RS00201) ISCA"},{"key":"3","author":"bell jr","year":"2005","journal-title":"Improved Automatic Testcase Synthesis for Performance Model Validation ICS"},{"key":"20","author":"joshi","year":"2006","journal-title":"Evaluating the Efficacy of Statistical Simulation for Design Space Exploration ISPASS"},{"key":"2","author":"eeckhout","year":"2004","journal-title":"Improved Control Flow in Statistical Simulation for Accurate and Efficient Processor Design Studies"},{"key":"1","author":"penry","year":"2006","journal-title":"Exploiting Parallelism and Structure to Accelerate the Simulation of Chip Multi-processors HPCA"},{"key":"10","author":"genbrugge","year":"2006","journal-title":"Accurate Memory Data Flow Modeling in Statistical Simulation ICS"},{"key":"7","author":"luk","year":"2005","journal-title":"Pin Building Customized Program Analysis Tools with Dynamic Instrumentation PLDI"},{"key":"6","article-title":"deconstructing and improving statistical simulation in hls","author":"bell jr","year":"2004","journal-title":"Workshop on Debunking Duplicating and Deconstructing"},{"key":"5","author":"joshi","year":"2006","journal-title":"Performance Cloning A Technique for Disseminating Proprietary Applications as Benchmarks ISWC"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/43.736182"},{"key":"9","year":"0","journal-title":"Boost C++ libraries"},{"key":"8","article-title":"evaluating non-deterministic multi-threaded commercial workloads","author":"alameldeen","year":"2002","journal-title":"Proceedings of the Computer Architecture Evaluation using Commercial Workloads"}],"event":{"name":"2008 IEEE International Symposium on Workload Characterization (IISWC)","location":"Seattle, WA, USA","start":{"date-parts":[[2008,9,14]]},"end":{"date-parts":[[2008,9,16]]}},"container-title":["2008 IEEE International Symposium on Workload Characterization"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4629859\/4636078\/04636101.pdf?arnumber=4636101","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,8,28]],"date-time":"2025-08-28T18:03:28Z","timestamp":1756404208000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/4636101\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2008,10]]},"references-count":24,"URL":"https:\/\/doi.org\/10.1109\/iiswc.2008.4636101","relation":{},"subject":[],"published":{"date-parts":[[2008,10]]}}}