{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,7]],"date-time":"2024-09-07T00:53:18Z","timestamp":1725670398103},"reference-count":51,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2017,10]]},"DOI":"10.1109\/iiswc.2017.8167773","type":"proceedings-article","created":{"date-parts":[[2017,12,7]],"date-time":"2017-12-07T18:28:15Z","timestamp":1512671295000},"page":"156-166","source":"Crossref","is-referenced-by-count":1,"title":["Work as a team or individual: Characterizing the system-level impacts of main memory partitioning"],"prefix":"10.1109","author":[{"given":"Eojin","family":"Lee","sequence":"first","affiliation":[]},{"given":"Jongwook","family":"Chung","sequence":"additional","affiliation":[]},{"given":"Daejin","family":"Jung","sequence":"additional","affiliation":[]},{"given":"Sukhan","family":"Lee","sequence":"additional","affiliation":[]},{"given":"Sheng","family":"Li","sequence":"additional","affiliation":[]},{"given":"Jung Ho","family":"Ahn","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/HOTCHIPS.2010.7480083"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1145\/1394608.1382128"},{"key":"ref33","article-title":"MICA: A Holistic Approach to Fast In-Memory Key-Value Storage","author":"lim","year":"2014","journal-title":"USENIX Symposium on Networked Systems Design and Implementation (NSDI)"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1145\/2749469.2750416"},{"key":"ref31","doi-asserted-by":"crossref","DOI":"10.1145\/360128.360132","article-title":"Eager Writeback - a Technique for Improving Bandwidth Utilization","author":"lee","year":"2000","journal-title":"Micro"},{"key":"ref30","article-title":"DRAM-Aware Last-Level Cache Writeback: Reducing Write-Caused Interference in Memory Systems","author":"lee","year":"2010","journal-title":"TR-HPS-2010&#x2013;002"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1145\/2155620.2155664"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1145\/2678373.2665698"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1145\/2370816.2370869"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1145\/2579672"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2012.6237032"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC.2011.6114191"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1145\/378993.379007"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2013.6557148"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/1654059.1654102"},{"journal-title":"High-bandwidth Memory (HBM) DRAM","year":"2013","key":"ref20"},{"journal-title":"Low Power Double Data Rate 4 (LPDDR4) Specification","year":"2014","key":"ref22"},{"journal-title":"DDR4 SDRAM Load Reduced DIMM (LRDIMM)","year":"2014","key":"ref21"},{"key":"ref24","article-title":"The Virtual Write Queue: Coordinating DRAM and Last-Level Cache Policies","author":"jeffrey","year":"2010","journal-title":"ISCA"},{"journal-title":"Wide I\/O 2 Specification","year":"2014","key":"ref23"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/LCA.2015.2495103"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2012.6168944"},{"key":"ref50","doi-asserted-by":"publisher","DOI":"10.1109\/RTAS.2014.6925999"},{"key":"ref51","doi-asserted-by":"publisher","DOI":"10.1145\/2678373.2665724"},{"key":"ref10","article-title":"Fairness via Source Throttling: A Configurable and High-Performance Fairness Substrate for Multi-Core Memory Systems","author":"eiman","year":"2010","journal-title":"ASPLOS"},{"journal-title":"Memcached A Distributed Memory Object Caching System","year":"2011","author":"fitzpatrick","key":"ref11"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/SAMOS.2014.6893198"},{"key":"ref12","article-title":"XOR-Schemes: A Flexible Data Organization in Parallel Memories","author":"frailong","year":"1985","journal-title":"International Conference on Parallel Processing (ICPP)"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/2304576.2304613"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/1241601.1241618"},{"journal-title":"Intel(R) Xeon(R) processor 7500 series datasheet","year":"2010","key":"ref15"},{"journal-title":"Accelerate Big Data Insights with the Intel Xeon Processor E7&#x2013;8800\/4800 v3 Product Families","year":"2013","key":"ref16"},{"journal-title":"Memory Systems Cache DRAM Disk","year":"2007","author":"jacob","key":"ref17"},{"journal-title":"Graphic Double Data Rate 5 (GDDR5) Specification","article-title":"JEDEC","year":"2009","key":"ref18"},{"journal-title":"DDR4 SDRAM Specification","year":"2012","key":"ref19"},{"key":"ref4","article-title":"Staged Memory Scheduling: Achieving High Performance and Scalability in Heterogeneous Systems","author":"ausavarungnirun","year":"2012","journal-title":"ISCA"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/1840845.1840930"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ICDE.2013.6544839"},{"key":"ref5","doi-asserted-by":"crossref","first-page":"319","DOI":"10.1145\/1854273.1854314","article-title":"Handling the problems and opportunities posed by multiple on-chip memory controllers","author":"awasthi","year":"2010","journal-title":"Proceedings of the 19th International Conference on Parallel Architectures and Compilation Techniques (PACT)"},{"key":"ref8","article-title":"A White Paper on the Benefits of Chipkill-Correct ECC for PC Server Main Memory","author":"dell","year":"1997","journal-title":"IBM Microelectronics Division"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/2485922.2485943"},{"key":"ref49","doi-asserted-by":"publisher","DOI":"10.1145\/2000064.2000100"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/2155620.2155663"},{"key":"ref46","article-title":"Knights Landing: 2nd Generation Intel","author":"sodani","year":"2015","journal-title":"Xeon Phi&#x201D; Proco-cessor &#x201D; in Hot Chips"},{"key":"ref45","article-title":"Ad-dressing Service Interruptions in Memory with Thread-to-Rank Assignment","author":"shevgoor","year":"2016","journal-title":"ISPASS"},{"key":"ref48","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1995.524546"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.1109\/SC.2014.91"},{"key":"ref42","article-title":"Hybrid Memory Cube","author":"pawlowski","year":"2011","journal-title":"Hot Chips"},{"key":"ref41","article-title":"Staged Reads: Mitigating the Impact of DRAM Writes on DRAM Reads","author":"niladrish","year":"2012","journal-title":"HPCA"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1145\/605397.605403"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2014.6853204"}],"event":{"name":"2017 IEEE International Symposium on Workload Characterization (IISWC)","start":{"date-parts":[[2017,10,1]]},"location":"Seattle, WA","end":{"date-parts":[[2017,10,3]]}},"container-title":["2017 IEEE International Symposium on Workload Characterization (IISWC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8122074\/8167743\/08167773.pdf?arnumber=8167773","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,8,29]],"date-time":"2023-08-29T15:23:19Z","timestamp":1693322599000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/8167773\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,10]]},"references-count":51,"URL":"https:\/\/doi.org\/10.1109\/iiswc.2017.8167773","relation":{},"subject":[],"published":{"date-parts":[[2017,10]]}}}