{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,7]],"date-time":"2024-09-07T05:20:09Z","timestamp":1725686409522},"reference-count":51,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2017,10]]},"DOI":"10.1109\/iiswc.2017.8167776","type":"proceedings-article","created":{"date-parts":[[2017,12,7]],"date-time":"2017-12-07T18:28:15Z","timestamp":1512671295000},"page":"187-196","source":"Crossref","is-referenced-by-count":8,"title":["Characterizing diverse handheld apps for customized hardware acceleration"],"prefix":"10.1109","author":[{"given":"Prasanna Venkatesh","family":"Rengasamy","sequence":"first","affiliation":[]},{"given":"Haibo","family":"Zhang","sequence":"additional","affiliation":[]},{"given":"Nachiappan","family":"Nachiappan","sequence":"additional","affiliation":[]},{"given":"Shulin","family":"Zhao","sequence":"additional","affiliation":[]},{"given":"Anand","family":"Sivasubramaniam","sequence":"additional","affiliation":[]},{"given":"Mahmut T.","family":"Kandemir","sequence":"additional","affiliation":[]},{"given":"Chita R.","family":"Das","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2005.854408"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/4.509850"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2011.5746251"},{"key":"ref32","article-title":"A 249Mpixel\/s HEVC Video-decoder Chip for Quad Full HD Applications","author":"huang","year":"2013","journal-title":"JSSC"},{"key":"ref31","article-title":"Intel AVX: New Frontiers in Performance Improvements and Energy Efficiency","author":"firasta","year":"2008","journal-title":"Intel White Paper"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/2.809248"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/L-CA.2011.4"},{"journal-title":"Vivado Design Suite HLx Editions - Accelerating High Level Design","article-title":"Xilinx","year":"2016","key":"ref36"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/12.931895"},{"journal-title":"Loop Invariant Code Motion","article-title":"LLVM","year":"2016","key":"ref34"},{"key":"ref28","article-title":"Qemu, a fast and portable dynamic translator","author":"bellard","year":"2005","journal-title":"ATC ser ATEC"},{"key":"ref27","article-title":"Automatic design of domain-specific instructions for low-power processors","author":"gonzlez-lvarez","year":"2015","journal-title":"ASAP"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2011.18"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/2678373.2665689"},{"journal-title":"Debate Specialized Architectures Languages and System Software Should Largely Supplant General-purpose Alternatives within the Next Decades","year":"2014","author":"wood","key":"ref1"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/2678373.2665749"},{"journal-title":"OpenMAX Integration Layer Application Programming Interface Specification Version 1 2 0 Provisional","article-title":"Khronos","year":"2011","key":"ref22"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2169689"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1145\/2024724.2024949"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1145\/3123939.3123948"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1145\/384286.264200"},{"journal-title":"reference manual","article-title":"Architecture Reference Manual","year":"2014","key":"ref25"},{"key":"ref50","doi-asserted-by":"publisher","DOI":"10.1145\/2897937.2897991"},{"key":"ref51","doi-asserted-by":"publisher","DOI":"10.1145\/2967938.2967940"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/2155620.2155623"},{"key":"ref11","article-title":"A High-performance Microarchitecture with Hardware-programmable Functional Units","author":"razdan","year":"1994","journal-title":"Micro"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/TITB.2005.854512"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/2749469.2750380"},{"key":"ref13","article-title":"The Renewed Case for the Reduced Instruction Set Computer: Avoiding ISA Bloat with Macro-Op Fusion for RISC-V","author":"celio","year":"2016","journal-title":"CoRR"},{"journal-title":"Tensilica Customizable Proc","year":"2017","key":"ref14"},{"journal-title":"SPEC CPU2006 Benchmarks","year":"2006","author":"henning","key":"ref15"},{"journal-title":"FPGCA","year":"0","author":"wittig","key":"ref16"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2016.7783752"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/2024716.2024718"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1145\/2637364.2591973"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/2908080.2908082"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2015.8"},{"key":"ref6","doi-asserted-by":"crossref","DOI":"10.1145\/2541940.2541967","article-title":"Di-anNao: A Small-footprint High-throughput Accelerator for Ubiquitous Machine-learning","author":"chen","year":"2014","journal-title":"ASPLOS"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/2897937.2897974"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/2830772.2830789"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2011.5749755"},{"key":"ref49","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2013.6691166"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2003.821545"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2014.7001346"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2010.40"},{"key":"ref48","doi-asserted-by":"publisher","DOI":"10.1145\/859618.859664"},{"journal-title":"The Cray-1 Computer System","year":"1978","author":"russell","key":"ref47"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/FPGA.1995.477415"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1999.765937"},{"key":"ref44","doi-asserted-by":"crossref","DOI":"10.1145\/329166.329185","article-title":"A Reconfigurable Multifunction Computing Cache Architecture","author":"kim","year":"2000","journal-title":"FPGA"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2010.5653632"}],"event":{"name":"2017 IEEE International Symposium on Workload Characterization (IISWC)","start":{"date-parts":[[2017,10,1]]},"location":"Seattle, WA","end":{"date-parts":[[2017,10,3]]}},"container-title":["2017 IEEE International Symposium on Workload Characterization (IISWC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8122074\/8167743\/08167776.pdf?arnumber=8167776","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,10,7]],"date-time":"2019-10-07T13:37:39Z","timestamp":1570455459000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/8167776\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,10]]},"references-count":51,"URL":"https:\/\/doi.org\/10.1109\/iiswc.2017.8167776","relation":{},"subject":[],"published":{"date-parts":[[2017,10]]}}}