{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,23]],"date-time":"2024-10-23T00:23:57Z","timestamp":1729643037904,"version":"3.28.0"},"reference-count":11,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2010,7]]},"DOI":"10.1109\/ijcnn.2010.5596547","type":"proceedings-article","created":{"date-parts":[[2010,10,19]],"date-time":"2010-10-19T14:58:15Z","timestamp":1287500295000},"page":"1-5","source":"Crossref","is-referenced-by-count":1,"title":["A low-power, high-resolution WTA utilizing translinear-loop pre-amplifier"],"prefix":"10.1109","author":[{"given":"Hung-Yi","family":"Hsieh","sequence":"first","affiliation":[]},{"given":"Kea-Tiong","family":"Tang","sequence":"additional","affiliation":[]},{"given":"Zen-Huan","family":"Tsai","sequence":"additional","affiliation":[]},{"given":"Hsin","family":"Chen","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"crossref","DOI":"10.7551\/mitpress\/1250.001.0001","article-title":"Analog VLSI: Circuits and Principles","author":"liu","year":"2002"},{"key":"ref3","article-title":"A neuromorphic VLSI device for implementing 2 D selective attention systems","volume":"12","year":"2001","journal-title":"IEEE Transactions on Neural Networks"},{"key":"ref10","first-page":"703","article-title":"Winnertake-all of O(n) complexity","author":"lazzaro","year":"1989","journal-title":"Advances in Neural Signal Processing Systems"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/81.662705"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1023\/A:1011208127849"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/81.386164"},{"key":"ref8","article-title":"A High-speed and High-Precision Winner-Select-Output (WSO) ASIC","volume":"45","author":"yu","year":"1998","journal-title":"IEEE Transactions on Nuclear Science"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1049\/el:19930606"},{"key":"ref2","first-page":"6","article-title":"High Speed Robust Current Sense Amplier for Nanoscale Memories:- A Winner Take All approach","author":"sundaram","year":"2006","journal-title":"VLSI Design 2006 Held jointly with 5th International Conference on Embedded Systems and Design 19th International Conference on"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2005.850433"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1049\/el:20063102"}],"event":{"name":"2010 International Joint Conference on Neural Networks (IJCNN)","start":{"date-parts":[[2010,7,18]]},"location":"Barcelona, Spain","end":{"date-parts":[[2010,7,23]]}},"container-title":["The 2010 International Joint Conference on Neural Networks (IJCNN)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5581822\/5595732\/05596547.pdf?arnumber=5596547","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,6,5]],"date-time":"2019-06-05T12:28:10Z","timestamp":1559737690000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5596547\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,7]]},"references-count":11,"URL":"https:\/\/doi.org\/10.1109\/ijcnn.2010.5596547","relation":{},"subject":[],"published":{"date-parts":[[2010,7]]}}}