{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,30]],"date-time":"2024-10-30T05:28:56Z","timestamp":1730266136065,"version":"3.28.0"},"reference-count":22,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2018,7]]},"DOI":"10.1109\/ijcnn.2018.8489378","type":"proceedings-article","created":{"date-parts":[[2018,10,19]],"date-time":"2018-10-19T22:25:09Z","timestamp":1539987909000},"page":"1-8","source":"Crossref","is-referenced-by-count":0,"title":["Socrates-D 2.0: A Low Power High Throughput Architecture for Deep Network Training"],"prefix":"10.1109","author":[{"given":"Yangjie","family":"Qi","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Raqibul","family":"Hasan","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Tarek M.","family":"Taha","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ICASSP.2013.6639343"},{"key":"ref11","first-page":"22","article-title":"CACTI 6.0: A tool to model large caches","author":"naveen","year":"2009","journal-title":"HP Laboratories"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2009.5090700"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ICECS.2014.7050069"},{"key":"ref14","first-page":"469","article-title":"McPAT: an integrated power, area, and timing modeling framework for multicore and manycore architectures","author":"sheng","year":"2009","journal-title":"Microarchitecture 2009 MICRO-42 42nd Annual IEEE\/ACM International Symposium on"},{"key":"ref15","first-page":"380","article-title":"Neurocube: A programmable digital neuromorphic architecture with high-density 3D memory","author":"duckhwan","year":"2016","journal-title":"2016 ACM\/IEEE 43rd Annual International Symposium on Computer Architecture (ISCA)"},{"year":"2017","key":"ref16"},{"journal-title":"Columbia University Image Library","year":"2017","key":"ref17"},{"journal-title":"Columbia University Image Library","year":"2017","key":"ref18"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1049\/ip-cds:20030607"},{"key":"ref4","first-page":"127","article-title":"Eyeriss: An energy-efficient reconfigurable accelerator for deep convolutional neural networks","author":"yu-hsin","year":"2017","journal-title":"IEEE J Solid State Circuits"},{"key":"ref3","first-page":"1","article-title":"NEUTRAMS: Neural network transformation and co-design under neuromorphic hardware constraints","author":"yu","year":"2016","journal-title":"Microarchitecture (MICRO) 2016 49th Annual IEEE\/ACM International Symposium on IEEE"},{"key":"ref6","first-page":"609","article-title":"Dadiannao: A machine-learning supercomputer","author":"yunji","year":"2014","journal-title":"Proc the annual IEEE\/ACM International Symposium on Microarchitecture"},{"key":"ref5","doi-asserted-by":"crossref","first-page":"668","DOI":"10.1126\/science.1254642","article-title":"A million spiking-neuron integrated circuit with a scalable communication network and interface","author":"merolla","year":"2014","journal-title":"Science 345"},{"key":"ref8","first-page":"14","article-title":"ISAAC: A convolutional neural network accelerator with in-situ analog arithmetic in crossbars","year":"2016","journal-title":"ACM SIGARCH Computer Architecture News"},{"key":"ref7","doi-asserted-by":"crossref","first-page":"255","DOI":"10.1145\/3007787.3001164","article-title":"RedEye: analog ConvNet image sensor architecture for continuous mobile vision","volume":"44","author":"robert","year":"2016","journal-title":"ACM SIGARCH Computer Architecture News"},{"key":"ref2","first-page":"243","article-title":"EIE: efficient inference engine on compressed deep neural network","author":"song","year":"2016","journal-title":"2016 ACM\/IEEE 43rd Annual International Symposium on Computer Architecture (ISCA)"},{"key":"ref1","doi-asserted-by":"crossref","first-page":"27","DOI":"10.1145\/3007787.3001140","article-title":"PRIME: a novel processing-in-memory architecture for neural network computation in ReRAM-based main memory","volume":"44","author":"ping","year":"2016","journal-title":"ACM SIGARCH Computer Architecture News"},{"journal-title":"Artificial Intelligence A Modern Approach","year":"2016","author":"russell","key":"ref9"},{"journal-title":"The MNIST Database of Handwritten Digits","year":"2017","key":"ref20"},{"key":"ref22","first-page":"1","article-title":"Socrates-D: Multicore Architecture for On-Line Learning","author":"yangjie","year":"2017","journal-title":"Rebooting Computing (ICRC) 2017 IEEE International Conference on"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.33"}],"event":{"name":"2018 International Joint Conference on Neural Networks (IJCNN)","start":{"date-parts":[[2018,7,8]]},"location":"Rio de Janeiro","end":{"date-parts":[[2018,7,13]]}},"container-title":["2018 International Joint Conference on Neural Networks (IJCNN)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8465565\/8488986\/08489378.pdf?arnumber=8489378","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,8,24]],"date-time":"2020-08-24T03:12:45Z","timestamp":1598238765000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8489378\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,7]]},"references-count":22,"URL":"https:\/\/doi.org\/10.1109\/ijcnn.2018.8489378","relation":{},"subject":[],"published":{"date-parts":[[2018,7]]}}}