{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,5,16]],"date-time":"2026-05-16T09:19:58Z","timestamp":1778923198256,"version":"3.51.4"},"reference-count":9,"publisher":"IEEE","license":[{"start":{"date-parts":[[2021,5,1]],"date-time":"2021-05-01T00:00:00Z","timestamp":1619827200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2021,5,1]],"date-time":"2021-05-01T00:00:00Z","timestamp":1619827200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2021,5]]},"DOI":"10.1109\/imw51353.2021.9439594","type":"proceedings-article","created":{"date-parts":[[2021,5,31]],"date-time":"2021-05-31T22:40:32Z","timestamp":1622500832000},"page":"1-4","source":"Crossref","is-referenced-by-count":10,"title":["Bringing in Cryogenics to Storage: Characteristics and Performance Improvement of 3D Flash Memory"],"prefix":"10.1109","author":[{"given":"Yuta","family":"Aiba","sequence":"first","affiliation":[{"name":"Institute of Memory Technology Research &#x0026; Development, Kioxia Corporation,Japan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hitomi","family":"Tanaka","sequence":"additional","affiliation":[{"name":"Institute of Memory Technology Research &#x0026; Development, Kioxia Corporation,Japan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Takashi","family":"Maeda","sequence":"additional","affiliation":[{"name":"Institute of Memory Technology Research &#x0026; Development, Kioxia Corporation,Japan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Keiichi","family":"Sawa","sequence":"additional","affiliation":[{"name":"Institute of Memory Technology Research &#x0026; Development, Kioxia Corporation,Japan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Fumie","family":"Kikushima","sequence":"additional","affiliation":[{"name":"Kioxia Corporation,Memory Div.,Japan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Masayuki","family":"Miura","sequence":"additional","affiliation":[{"name":"Kioxia Corporation,Memory Div.,Japan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Toshio","family":"Fujisawa","sequence":"additional","affiliation":[{"name":"Institute of Memory Technology Research &#x0026; Development, Kioxia Corporation,Japan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Mie","family":"Matsuo","sequence":"additional","affiliation":[{"name":"Institute of Memory Technology Research &#x0026; Development, Kioxia Corporation,Japan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hideto","family":"Horii","sequence":"additional","affiliation":[{"name":"Institute of Memory Technology Research &#x0026; Development, Kioxia Corporation,Japan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hideko","family":"Mukaida","sequence":"additional","affiliation":[{"name":"Kioxia Corporation,Memory Div.,Japan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Tomoya","family":"Sanuki","sequence":"additional","affiliation":[{"name":"Institute of Memory Technology Research &#x0026; Development, Kioxia Corporation,Japan"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/3307650.3322219"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/IMW.2018.8388826"},{"key":"ref6","article-title":"Cryogenic Operation of 3D Flash Memory for New Applications and Bit Cost Scaling with 6-Bit per Cell (HLC) and Beyond","author":"aiba","year":"2021","journal-title":"EDTM"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2019.2933504"},{"key":"ref8","first-page":"232t","article-title":"Performance of GAA poly-Si nanosheet (2nm) channel of junctionless transistors with ideal subthreshold slope","author":"chen","year":"0","journal-title":"VLSI Symp Tech"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2017.2675160"},{"key":"ref2","first-page":"1","article-title":"Cold CMOS as a Power-Performance-Reliability Booster for Advanced FinFETs","author":"chiang","year":"0","journal-title":"VLSI Symp Tech"},{"key":"ref9","first-page":"1","article-title":"Comprehensive evaluation of early retention (fast charge loss within a few seconds) characteristics in tube-type 3-D NAND flash memory","author":"choi","year":"0","journal-title":"VLSI Symp Tech"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/16.30952"}],"event":{"name":"2021 IEEE International Memory Workshop (IMW)","location":"Dresden, Germany","start":{"date-parts":[[2021,5,16]]},"end":{"date-parts":[[2021,5,19]]}},"container-title":["2021 IEEE International Memory Workshop (IMW)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9439548\/9439588\/09439594.pdf?arnumber=9439594","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,8,2]],"date-time":"2022-08-02T23:53:45Z","timestamp":1659484425000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9439594\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,5]]},"references-count":9,"URL":"https:\/\/doi.org\/10.1109\/imw51353.2021.9439594","relation":{},"subject":[],"published":{"date-parts":[[2021,5]]}}}