{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,30]],"date-time":"2024-10-30T05:50:13Z","timestamp":1730267413168,"version":"3.28.0"},"reference-count":10,"publisher":"IEEE","license":[{"start":{"date-parts":[[2021,5,1]],"date-time":"2021-05-01T00:00:00Z","timestamp":1619827200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2021,5,1]],"date-time":"2021-05-01T00:00:00Z","timestamp":1619827200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2021,5,1]],"date-time":"2021-05-01T00:00:00Z","timestamp":1619827200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2021,5]]},"DOI":"10.1109\/imw51353.2021.9439625","type":"proceedings-article","created":{"date-parts":[[2021,5,31]],"date-time":"2021-05-31T22:40:32Z","timestamp":1622500832000},"page":"1-4","source":"Crossref","is-referenced-by-count":2,"title":["1.5-nm Node Surrounding Gate Transistor (SGT)-SRAM Cell with Staggered Pillar and Self-Aligned Process for Gate, Bottom Contact, and Pillar"],"prefix":"10.1109","author":[{"given":"Yisuo","family":"Li","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kenichi","family":"Kanazawa","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Tetsuo","family":"Izawa","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Koji","family":"Sakui","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Georg","family":"Strof","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Oskar","family":"Baumgartner","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Gerhard","family":"Rzepa","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Markus","family":"Karner","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Zlatan","family":"Stanojevic","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Nozomu","family":"Harada","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Fujio","family":"Masuoka","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM19573.2019.8993626"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.23919\/VLSIT.2019.8776513"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/SISPAD.2018.8551632"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1117\/12.915695"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.23919\/VLSIT.2019.8776532"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2015.7409631"},{"key":"ref7","first-page":"917","article-title":"Advanced Node DTCO in the EUV Era","volume":"20","author":"wei","year":"2020","journal-title":"Technical Digest of IEDM"},{"key":"ref2","first-page":"595","article-title":"Silicon-on-insulator ‘gate-all-around device’","volume":"90","author":"colinge","year":"1990","journal-title":"Technical Digest of IEDM"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ESSDERC.2018.8486887"},{"key":"ref1","first-page":"913","article-title":"DTCO Launches Moore's Law Over the Feature Scaling Wall","volume":"20","author":"moroz","year":"2020","journal-title":"Technical Digest of IEDM"}],"event":{"name":"2021 IEEE International Memory Workshop (IMW)","start":{"date-parts":[[2021,5,16]]},"location":"Dresden, Germany","end":{"date-parts":[[2021,5,19]]}},"container-title":["2021 IEEE International Memory Workshop (IMW)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9439548\/9439588\/09439625.pdf?arnumber=9439625","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,5,10]],"date-time":"2022-05-10T15:41:47Z","timestamp":1652197307000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9439625\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,5]]},"references-count":10,"URL":"https:\/\/doi.org\/10.1109\/imw51353.2021.9439625","relation":{},"subject":[],"published":{"date-parts":[[2021,5]]}}}