{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,8,26]],"date-time":"2026-08-26T15:54:58Z","timestamp":1787759698732,"version":"build-2784847793"},"reference-count":5,"publisher":"IEEE","license":[{"start":{"date-parts":[[2024,5,12]],"date-time":"2024-05-12T00:00:00Z","timestamp":1715472000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2024,5,12]],"date-time":"2024-05-12T00:00:00Z","timestamp":1715472000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2024,5,12]]},"DOI":"10.1109\/imw59701.2024.10536951","type":"proceedings-article","created":{"date-parts":[[2024,5,24]],"date-time":"2024-05-24T17:19:11Z","timestamp":1716571151000},"page":"1-4","source":"Crossref","is-referenced-by-count":3,"title":["Novel Multi-Level Coding and Architecture Enabling Fast Random Access for Flash Memory"],"prefix":"10.1109","author":[{"given":"Noboru","family":"Shibata","sequence":"first","affiliation":[{"name":"Kioxia Corporation,Institute of Memory Technology Research &#x0026; Development,Japan"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Hironori","family":"Uchikawa","sequence":"additional","affiliation":[{"name":"Kioxia Corporation,Institute of Memory Technology Research &#x0026; Development,Japan"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Taira","family":"Shibuya","sequence":"additional","affiliation":[{"name":"Kioxia Corporation,Memory Div.,Japan"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Hirofumi","family":"Inoue","sequence":"additional","affiliation":[{"name":"Kioxia Corporation,Memory Development Strategy Div.,Japan"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/isscc19947.2020.9063154"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.23919\/VLSITechnologyandCir57934.2023.10185237"},{"key":"ref3","article-title":"Coding scheme for optimizing random I\/O performance","volume-title":"Proc. NVMW2013","author":"Sharon"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TCOMM.2016.2538219"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/IMW56887.2023.10145980"}],"event":{"name":"2024 IEEE International Memory Workshop (IMW)","location":"Seoul, Korea, Republic of","start":{"date-parts":[[2024,5,12]]},"end":{"date-parts":[[2024,5,15]]}},"container-title":["2024 IEEE International Memory Workshop (IMW)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/10536936\/10536916\/10536951.pdf?arnumber=10536951","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,5,25]],"date-time":"2024-05-25T04:50:17Z","timestamp":1716612617000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10536951\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,5,12]]},"references-count":5,"URL":"https:\/\/doi.org\/10.1109\/imw59701.2024.10536951","relation":{},"subject":[],"published":{"date-parts":[[2024,5,12]]}}}