{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,4]],"date-time":"2026-03-04T17:04:29Z","timestamp":1772643869036,"version":"3.50.1"},"reference-count":11,"publisher":"IEEE","license":[{"start":{"date-parts":[[2025,5,18]],"date-time":"2025-05-18T00:00:00Z","timestamp":1747526400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2025,5,18]],"date-time":"2025-05-18T00:00:00Z","timestamp":1747526400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2025,5,18]]},"DOI":"10.1109\/imw61990.2025.11026939","type":"proceedings-article","created":{"date-parts":[[2025,6,12]],"date-time":"2025-06-12T17:40:04Z","timestamp":1749750004000},"page":"1-4","source":"Crossref","is-referenced-by-count":1,"title":["Crossed Bit Line (CBL) Architecture in 3D Flash Memory CMOS Directly Bonded to Array (CBA) Structure"],"prefix":"10.1109","author":[{"given":"H.","family":"Maejima","sequence":"first","affiliation":[{"name":"Kioxia Corporation,Memory Div.,Yokohama, Kanagawa,Japan"}]},{"given":"K.","family":"Isobe","sequence":"additional","affiliation":[{"name":"Kioxia Corporation,Memory Div.,Yokohama, Kanagawa,Japan"}]},{"given":"N.","family":"Okada","sequence":"additional","affiliation":[{"name":"Kioxia Corporation,Memory Div.,Yokohama, Kanagawa,Japan"}]},{"given":"M.","family":"Unno","sequence":"additional","affiliation":[{"name":"Kioxia Corporation,Memory Div.,Yokohama, Kanagawa,Japan"}]},{"given":"T.","family":"Hashimoto","sequence":"additional","affiliation":[{"name":"Kioxia Corporation,Memory Div.,Yokohama, Kanagawa,Japan"}]},{"given":"T.","family":"Utsumi","sequence":"additional","affiliation":[{"name":"Kioxia Corporation,Memory Div.,Yokohama, Kanagawa,Japan"}]},{"given":"T.","family":"Hisada","sequence":"additional","affiliation":[{"name":"Kioxia Corporation,Memory Div.,Yokohama, Kanagawa,Japan"}]},{"given":"K.","family":"Maruyama","sequence":"additional","affiliation":[{"name":"Kioxia Corporation,Memory Div.,Yokohama, Kanagawa,Japan"}]},{"given":"T.","family":"Kouchi","sequence":"additional","affiliation":[{"name":"Kioxia Corporation,Memory Div.,Yokohama, Kanagawa,Japan"}]},{"given":"T.","family":"Kotani","sequence":"additional","affiliation":[{"name":"Kioxia Corporation,Memory Div.,Yokohama, Kanagawa,Japan"}]},{"given":"H.","family":"Shiga","sequence":"additional","affiliation":[{"name":"Kioxia Corporation,Memory Div.,Yokohama, Kanagawa,Japan"}]},{"given":"O.","family":"Kwon","sequence":"additional","affiliation":[{"name":"Sandisk Technologies Inc,Milpitas,CA,USA"}]},{"given":"A.","family":"Ganguly","sequence":"additional","affiliation":[{"name":"Sandisk Technologies Inc,Milpitas,CA,USA"}]},{"given":"Y.","family":"Wu","sequence":"additional","affiliation":[{"name":"Sandisk Technologies Inc,Milpitas,CA,USA"}]},{"given":"H.","family":"Yabe","sequence":"additional","affiliation":[{"name":"Sandisk Technologies GK,Fujisawa, Kanagawa,Japan"}]},{"given":"I.","family":"Lu","sequence":"additional","affiliation":[{"name":"Sandisk Technologies Inc,Milpitas,CA,USA"}]},{"given":"F.","family":"Toyama","sequence":"additional","affiliation":[{"name":"Sandisk Technologies Inc,Milpitas,CA,USA"}]},{"given":"N.","family":"Morozumi","sequence":"additional","affiliation":[{"name":"Sandisk Technologies GK,Fujisawa, Kanagawa,Japan"}]},{"given":"M.","family":"Takehara","sequence":"additional","affiliation":[{"name":"Sandisk Technologies GK,Fujisawa, Kanagawa,Japan"}]},{"given":"T.","family":"Ariki","sequence":"additional","affiliation":[{"name":"Sandisk Technologies GK,Fujisawa, Kanagawa,Japan"}]},{"given":"I.","family":"Yoon","sequence":"additional","affiliation":[{"name":"Sandisk Technologies Inc,Milpitas,CA,USA"}]}],"member":"263","reference":[{"key":"ref1","first-page":"14","volume-title":"Symp. on VLSI","author":"Tanaka"},{"key":"ref2","first-page":"334","author":"Park","year":"2014","journal-title":"ISSCC"},{"key":"ref3","first-page":"336","author":"Maejima","year":"2018","journal-title":"ISSCC"},{"key":"ref4","first-page":"142","author":"Tanaka","year":"2016","journal-title":"ISSCC"},{"key":"ref5","first-page":"428","author":"Higuchi","year":"2021","journal-title":"ISSCC"},{"key":"ref6","first-page":"978","volume-title":"Symp. on VLSI","author":"Sako"},{"key":"ref7","volume":"35-2","author":"Kobayashi","year":"2023","journal-title":"IEDM"},{"key":"ref8","volume-title":"IITC","author":"Kobayashi"},{"key":"ref9","first-page":"1920","author":"Johnson","year":"2003","journal-title":"ISSCC"},{"key":"ref10","volume-title":"Patent","author":"Maejima","year":"2011"},{"key":"ref11","first-page":"210","author":"Shibata","year":"2019","journal-title":"ISSCC"}],"event":{"name":"2025 IEEE International Memory Workshop (IMW)","location":"Monterey, CA, USA","start":{"date-parts":[[2025,5,18]]},"end":{"date-parts":[[2025,5,21]]}},"container-title":["2025 IEEE International Memory Workshop (IMW)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/11026918\/11026883\/11026939.pdf?arnumber=11026939","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,13]],"date-time":"2025-06-13T05:46:11Z","timestamp":1749793571000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11026939\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,5,18]]},"references-count":11,"URL":"https:\/\/doi.org\/10.1109\/imw61990.2025.11026939","relation":{},"subject":[],"published":{"date-parts":[[2025,5,18]]}}}