{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,12]],"date-time":"2026-02-12T15:27:59Z","timestamp":1770910079729,"version":"3.50.1"},"reference-count":10,"publisher":"IEEE","license":[{"start":{"date-parts":[[2025,5,18]],"date-time":"2025-05-18T00:00:00Z","timestamp":1747526400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2025,5,18]],"date-time":"2025-05-18T00:00:00Z","timestamp":1747526400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2025,5,18]]},"DOI":"10.1109\/imw61990.2025.11026972","type":"proceedings-article","created":{"date-parts":[[2025,6,12]],"date-time":"2025-06-12T17:40:04Z","timestamp":1749750004000},"page":"1-4","source":"Crossref","is-referenced-by-count":1,"title":["Low write power and Field-free sub-ns write speed SOT-MRAM cell with Design Technology of Canted SOT structure and Magnetic Anisotropy for NVM"],"prefix":"10.1109","author":[{"given":"T. V. A.","family":"Nguyen","sequence":"first","affiliation":[{"name":"Tohoku Univ,Center for Innovative Integrated Electronic Systems"}]},{"given":"H.","family":"Naganuma","sequence":"additional","affiliation":[{"name":"Tohoku Univ,Center for Innovative Integrated Electronic Systems"}]},{"given":"H.","family":"Honjo","sequence":"additional","affiliation":[{"name":"Tohoku Univ,Center for Innovative Integrated Electronic Systems"}]},{"given":"Y.","family":"Sato","sequence":"additional","affiliation":[{"name":"Tohoku Univ,Center for Innovative Integrated Electronic Systems"}]},{"given":"T.","family":"Tanigawa","sequence":"additional","affiliation":[{"name":"Tohoku Univ,Center for Innovative Integrated Electronic Systems"}]},{"given":"S.","family":"Ikeda","sequence":"additional","affiliation":[{"name":"Tohoku Univ,Center for Innovative Integrated Electronic Systems"}]},{"given":"T.","family":"Endoh","sequence":"additional","affiliation":[{"name":"Tohoku Univ,Center for Innovative Integrated Electronic Systems"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM19573.2019.8993443"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/VLSITechnologyandCir46769.2022.9830149"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM45741.2023.10413749"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2016.7573379"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2018.8502269"},{"key":"ref6","first-page":"1","article-title":"BEOL compatible high retention perpendicular SOT-MRAM device for SRAM replacement and machine learning","volume-title":"2021 Symposium on VLSI Technology","author":"Couet"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.23919\/VLSIC.2019.8778100"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1038\/nmat2804"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1063\/9.0000789"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1016\/j.jmmm.2021.167757"}],"event":{"name":"2025 IEEE International Memory Workshop (IMW)","location":"Monterey, CA, USA","start":{"date-parts":[[2025,5,18]]},"end":{"date-parts":[[2025,5,21]]}},"container-title":["2025 IEEE International Memory Workshop (IMW)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/11026918\/11026883\/11026972.pdf?arnumber=11026972","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,13]],"date-time":"2025-06-13T05:32:00Z","timestamp":1749792720000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11026972\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,5,18]]},"references-count":10,"URL":"https:\/\/doi.org\/10.1109\/imw61990.2025.11026972","relation":{},"subject":[],"published":{"date-parts":[[2025,5,18]]}}}