{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,22]],"date-time":"2024-10-22T18:06:17Z","timestamp":1729620377693,"version":"3.28.0"},"reference-count":27,"publisher":"IEEE Comput. Soc.","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/intera.2003.1192353","type":"proceedings-article","created":{"date-parts":[[2003,8,27]],"date-time":"2003-08-27T11:41:06Z","timestamp":1061984466000},"page":"27-36","source":"Crossref","is-referenced-by-count":0,"title":["Procedure cloning and integration for converting parallelism from coarse to fine grain"],"prefix":"10.1109","author":[{"family":"Won So","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"A.","family":"Dean","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"journal-title":"The Multiscalar Architecture","year":"1993","author":"franklin","key":"ref10"},{"key":"ref11","doi-asserted-by":"crossref","first-page":"2","DOI":"10.1117\/12.334763","article-title":"Understanding multimedia application characteristics for designing programmable media processors","volume":"3655","author":"fritts","year":"1999","journal-title":"Proceedings of SPIE"},{"journal-title":"Managing interprocedural optimization","year":"1991","author":"hall","key":"ref12"},{"key":"ref13","article-title":"Multimedia communications: Applications","author":"halsall","year":"2001","journal-title":"Networks Protocols and Standarda"},{"journal-title":"Region-Based Compilation","year":"1996","author":"hank","key":"ref14"},{"key":"ref15","first-page":"650","article-title":"Interprocedural analysis for parallelization: Design and experience","author":"hall","year":"1995","journal-title":"Proceedings of the Seventh SIAM Conference on Parallel Processing for Scientific Computing"},{"volume":"i iv","journal-title":"Rev 1 1 Intel Corp","year":"2000","key":"ref16"},{"journal-title":"Intel Corp","year":"2001","key":"ref17"},{"key":"ref18","article-title":"Mediabench: a tool for evaluating and synthesizing multimedia and communications systems","author":"lee","year":"1997","journal-title":"Proc 30th Ann ACM\/IEEE Int l Symp Microarchitecture"},{"journal-title":"IA-64 Linux Kernel Design and Implementation","year":"2002","author":"mosberger","key":"ref19"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/207110.207119"},{"key":"ref27","article-title":"DSPstone: A DSP-oriented benchmarking methodology","author":"zivojnovi'c","year":"1994","journal-title":"Proc ICSPAT 94"},{"journal-title":"Ren Rodriguez FIAT A Framework for Interprocedural Analysis and Transformation","year":"1995","author":"carle","key":"ref3"},{"key":"ref6","doi-asserted-by":"crossref","DOI":"10.1109\/INTERA.2002.995838","article-title":"Compiling for Fine-Grain Concurrency: Planning and Performing Software Thread Integration","author":"dean","year":"2002","journal-title":"6th Annual Workshop on Interaction between Compilers and Computer Architectures (INTERACT-6 in conjunction with HPCA 8)"},{"article-title":"Software Thread Integration for Hardware to Software Migration","year":"2000","author":"dean","key":"ref5"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/321312.321314"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/REAL.1998.739760"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1016\/0096-0551(93)90005-L"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/24039.24041"},{"key":"ref1","article-title":"An Overview of the PARADIGM Compiler for Distributed-Memory Multicomputers","volume":"28","author":"banerjee","year":"0","journal-title":"IEEE Computer"},{"article-title":"Exploiting Multi-Grained Parallelism for Multiple-Instruction Stream Architectures","year":"1997","author":"newburn","key":"ref20"},{"key":"ref22","first-page":"414","article-title":"Multiscalar processors","author":"sohi","year":"1995","journal-title":"Proceedings 22nd Annual International Symposium on Computer Architecture ISCA"},{"journal-title":"Trimaran &#x2013; an infrastructure for compiler research in instruction-level parallelism &#x2013; user manual","year":"1998","author":"nene","key":"ref21"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1145\/103085.103089"},{"article-title":"Software Thread Integration For Converting TLP To ILP on VLIW\/EPIC Architectures","year":"2002","author":"so","key":"ref23"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1145\/106972.106976"},{"journal-title":"Procedure restructuring for ambitious optimization","year":"2002","author":"way","key":"ref25"}],"event":{"name":"Interact 7 - 7th IEEE Workshop on Interaction between Compilers and Computer Architectures","acronym":"INTERA-03","location":"Anaheim, CA, USA"},"container-title":["Seventh Workshop on Interaction Between Compilers and Computer Architectures, 2003. INTERACT-7 2003. Proceedings."],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8483\/26739\/01192353.pdf?arnumber=1192353","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,15]],"date-time":"2017-06-15T20:09:10Z","timestamp":1497557350000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1192353\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":27,"URL":"https:\/\/doi.org\/10.1109\/intera.2003.1192353","relation":{},"subject":[]}}