{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,23]],"date-time":"2024-10-23T08:45:17Z","timestamp":1729673117608,"version":"3.28.0"},"reference-count":12,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2009,6]]},"DOI":"10.1109\/iolts.2009.5195979","type":"proceedings-article","created":{"date-parts":[[2009,8,11]],"date-time":"2009-08-11T15:37:37Z","timestamp":1250005057000},"page":"29-34","source":"Crossref","is-referenced-by-count":7,"title":["Comparing transient-fault effects on synchronous and on asynchronous circuits"],"prefix":"10.1109","author":[{"given":"R. Possamai","family":"Bastos","sequence":"first","affiliation":[]},{"given":"Y.","family":"Monnet","sequence":"additional","affiliation":[]},{"given":"G.","family":"Sicard","sequence":"additional","affiliation":[]},{"given":"F.","family":"Kastensmidt","sequence":"additional","affiliation":[]},{"given":"M.","family":"Renaudin","sequence":"additional","affiliation":[]},{"given":"R.","family":"Reis","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/VTEST.1999.766651"},{"key":"2","first-page":"228","article-title":"high-security smartcards","author":"renaudin","year":"2004","journal-title":"Proc DATE"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/RADECS.2005.4365571"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/TDSC.2004.14"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/23.903816"},{"key":"6","doi-asserted-by":"crossref","DOI":"10.29292\/jics.v1i1.249","article-title":"asynchronous aes crypto-processor including secured and optimized blocks","volume":"1","author":"bouesse","year":"2004","journal-title":"JICS"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2006.143"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2005.119"},{"key":"9","doi-asserted-by":"crossref","first-page":"511","DOI":"10.1023\/B:JETT.0000042515.67579.c1","article-title":"a new approach to the analysis of single event transients in vlsi circuits","volume":"20","author":"sonza reorda","year":"2004","journal-title":"Journal of Electronic Testing Theory and Applications"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1023\/B:JETT.0000039608.48856.33"},{"key":"11","first-page":"863","article-title":"asynchronous circuits transient faults sensitivity evaluation","author":"monnet","year":"2005","journal-title":"Proc DAC"},{"key":"12","first-page":"146","article-title":"technology mapping for area optimised quasi delay in-sensitive circuits","author":"folco","year":"2005","journal-title":"Proc VLSI-SOC"}],"event":{"name":"2009 15th IEEE International On-Line Testing Symposium (IOLTS 2009)","start":{"date-parts":[[2009,6,24]]},"location":"Sesimbra-Lisbon, Portugal","end":{"date-parts":[[2009,6,26]]}},"container-title":["2009 15th IEEE International On-Line Testing Symposium"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5176124\/5195974\/05195979.pdf?arnumber=5195979","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,10,9]],"date-time":"2021-10-09T11:19:02Z","timestamp":1633778342000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5195979\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2009,6]]},"references-count":12,"URL":"https:\/\/doi.org\/10.1109\/iolts.2009.5195979","relation":{},"subject":[],"published":{"date-parts":[[2009,6]]}}}