{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,7]],"date-time":"2024-09-07T01:23:40Z","timestamp":1725672220473},"reference-count":13,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2010,7]]},"DOI":"10.1109\/iolts.2010.5560219","type":"proceedings-article","created":{"date-parts":[[2010,9,7]],"date-time":"2010-09-07T20:30:39Z","timestamp":1283891439000},"page":"141-146","source":"Crossref","is-referenced-by-count":4,"title":["Cross-BIC architecture for single and multiple SEU detection enhancement in SRAM memories"],"prefix":"10.1109","author":[{"given":"S. A.","family":"Bota","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"G.","family":"Torrens","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"B.","family":"Alorda","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"J.","family":"Verd","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"J.","family":"Segura","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/IOLTS.2006.35"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TDMR.2005.855684"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2007.378282"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/IOLTS.2005.12"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/23.983155"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TDMR.2005.855790"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/23.819103"},{"key":"ref5","doi-asserted-by":"crossref","first-page":"592","DOI":"10.1109\/DATE.2005.54","article-title":"An Efficient BICS design for SEUs Detection and correction in semiconductor memories","author":"gill","year":"2005","journal-title":"Design Automation and Test in Europe 2005 proc"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/IOLTS.2008.36"},{"key":"ref7","first-page":"62","article-title":"Evaluating fault coverage of bulk built-in current sensor for soft errors in combinational and sequential logic","author":"neto","year":"2005","journal-title":"SBCCI '05 Proc 18th Ann Symp Integrated Circuits and System Design"},{"key":"ref2","doi-asserted-by":"crossref","first-page":"33","DOI":"10.1109\/IRPS.1978.362815","article-title":"A New Physical Mechanism for Soft Errors in Dynamic Memories","author":"may","year":"1978","journal-title":"Proc 16th Annual Reliability Physics Symp"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2003.821593"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/IOLTS.2005.59"}],"event":{"name":"2010 IEEE 16th International On-Line Testing Symposium (IOLTS 2010)","start":{"date-parts":[[2010,7,5]]},"location":"Corfu, Greece","end":{"date-parts":[[2010,7,7]]}},"container-title":["2010 IEEE 16th International On-Line Testing Symposium"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5550907\/5560185\/05560219.pdf?arnumber=5560219","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,6,4]],"date-time":"2019-06-04T02:41:31Z","timestamp":1559616091000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5560219\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,7]]},"references-count":13,"URL":"https:\/\/doi.org\/10.1109\/iolts.2010.5560219","relation":{},"subject":[],"published":{"date-parts":[[2010,7]]}}}