{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,23]],"date-time":"2024-10-23T05:42:43Z","timestamp":1729662163526,"version":"3.28.0"},"reference-count":27,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2014,7]]},"DOI":"10.1109\/iolts.2014.6873661","type":"proceedings-article","created":{"date-parts":[[2014,8,19]],"date-time":"2014-08-19T17:48:18Z","timestamp":1408470498000},"page":"7-12","source":"Crossref","is-referenced-by-count":0,"title":["Comparative study of defect-tolerant multiplexers for FPGAs"],"prefix":"10.1109","author":[{"given":"Arwa","family":"Ben Dhia","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Mariem","family":"Slimani","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Lirida","family":"Naviner","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"journal-title":"Mentor Graphics Tessent Cell Model Gen Tool","year":"0","author":"graphics","key":"19"},{"key":"17","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2009.5272319"},{"key":"18","doi-asserted-by":"publisher","DOI":"10.1109\/ICETET.2012.51"},{"key":"15","doi-asserted-by":"publisher","DOI":"10.1109\/DFT.2010.19"},{"key":"16","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2012.2213102"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2005.1568545"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1109\/ICECS.2012.6463643"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/AHS.2011.5963921"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/DDECS.2010.5491763"},{"key":"21","doi-asserted-by":"publisher","DOI":"10.1109\/IJCNN.2006.247183"},{"key":"20","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.1984.1156629"},{"key":"22","article-title":"A defect-tolerant multiplexer using differential logic for FPGAs","author":"dhia","year":"2014","journal-title":"IEEE International Conference Mixed Design of Integrated Circuits and Systems (MIXDES)"},{"key":"23","doi-asserted-by":"publisher","DOI":"10.1109\/ICICDT.2014.6838602"},{"key":"24","doi-asserted-by":"publisher","DOI":"10.1016\/j.microrel.2013.06.014"},{"key":"25","doi-asserted-by":"publisher","DOI":"10.1016\/j.microrel.2009.08.001"},{"key":"26","doi-asserted-by":"publisher","DOI":"10.1109\/NEWCAS.2010.5603933"},{"key":"27","doi-asserted-by":"crossref","first-page":"288","DOI":"10.1109\/TVLSI.2004.824300","article-title":"The effect of LUT and cluster size on deep-submicron FPGA performance and density","volume":"12","author":"ahmed","year":"2004","journal-title":"Very Large Scale Integration (VLSI) Systems IEEE Transactions on"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2006.32"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2010.48"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/IOLTS.2006.36"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1007\/BF03219903"},{"key":"7","first-page":"881","article-title":"A single fpga embedded framework for secondary user in cognitive network","author":"lu","year":"2010","journal-title":"Communication Technology (ICCT) 2010 12th IEEE International Conference on"},{"key":"6","first-page":"592","article-title":"Multiple faults: Modeling, simulation and test","author":"kim","year":"2002","journal-title":"Design Automation Conference 2002 Proceedings of ASP-DAC 2002 7th Asia and South Pacific and the 15th International Conference on VLSI Design Proceedings"},{"journal-title":"Essentials of Electronic Testing for Digital Memory and Mixed-Signal VLSI Circuits","year":"2000","author":"bushnell","key":"5"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/ASMC.2003.1194504"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/IOLTS.2006.13"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1016\/j.asr.2010.08.035"}],"event":{"name":"2014 IEEE 20th International On-Line Testing Symposium (IOLTS)","start":{"date-parts":[[2014,7,7]]},"location":"Platja d'Aro, Girona, Spain","end":{"date-parts":[[2014,7,9]]}},"container-title":["2014 IEEE 20th International On-Line Testing Symposium (IOLTS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6867432\/6873658\/06873661.pdf?arnumber=6873661","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,22]],"date-time":"2017-06-22T14:59:37Z","timestamp":1498143577000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6873661\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,7]]},"references-count":27,"URL":"https:\/\/doi.org\/10.1109\/iolts.2014.6873661","relation":{},"subject":[],"published":{"date-parts":[[2014,7]]}}}