{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,8]],"date-time":"2024-09-08T00:41:43Z","timestamp":1725756103499},"reference-count":16,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2014,7]]},"DOI":"10.1109\/iolts.2014.6873681","type":"proceedings-article","created":{"date-parts":[[2014,8,19]],"date-time":"2014-08-19T17:48:18Z","timestamp":1408470498000},"page":"111-115","source":"Crossref","is-referenced-by-count":13,"title":["Validation of a tool for estimating the effects of soft-errors on modern SRAM-based FPGAs"],"prefix":"10.1109","author":[{"given":"Marco","family":"Desogus","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Luca","family":"Sterpone","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"David Merodio","family":"Codinachs","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"15","article-title":"Estimation of mean time between failure caused by single event upset","author":"sundararajan","year":"2005","journal-title":"Xilinx Application Notes"},{"key":"16","doi-asserted-by":"publisher","DOI":"10.1109\/23.658966"},{"key":"13","doi-asserted-by":"crossref","first-page":"129","DOI":"10.1109\/OLT.2003.1214379","article-title":"A fault injection tool for SRAM-based FPGAs","author":"alderighi","year":"2003","journal-title":"Proc 9th IEEE On-Line Testing Symp"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1109\/OLT.2004.1319668"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2006.880937"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2007.910122"},{"key":"3","article-title":"Triple module redundancy design techniques for virtex FPGAs","author":"carmichael","year":"2001","journal-title":"Xilinx Application Notes"},{"journal-title":"ARM Cortex?-M0 Devices Generic User Guide Copyright \ufffd","year":"2009","key":"2"},{"journal-title":"ARM Cortex-M0 Design Start System Design Example Design Kit","year":"2012","key":"1"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2006.82"},{"key":"7","first-page":"275","article-title":"A fault injection analysis of virtex FPGA TMR design methodology","author":"lima","year":"2001","journal-title":"Proc IEEE European Conf Radiation and Its Effect on Components and Systems"},{"journal-title":"Digilent Genesys? Board Reference Manual","year":"2013","key":"6"},{"journal-title":"Fault-Tolerant Computer System Design","year":"0","author":"pradhan","key":"5"},{"journal-title":"Correcting Single-Event Upsets Through Virtex Partial Reconfiguration","year":"2000","key":"4"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2005.860745"},{"key":"8","article-title":"An analytical approach for soft error rate estimation of SRAM-based FPGAs","author":"asadi","year":"2004","journal-title":"Military and Aerospace Applications Programmable Logic Devices Conf"}],"event":{"name":"2014 IEEE 20th International On-Line Testing Symposium (IOLTS)","start":{"date-parts":[[2014,7,7]]},"location":"Platja d'Aro, Girona, Spain","end":{"date-parts":[[2014,7,9]]}},"container-title":["2014 IEEE 20th International On-Line Testing Symposium (IOLTS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6867432\/6873658\/06873681.pdf?arnumber=6873681","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,22]],"date-time":"2017-06-22T14:59:36Z","timestamp":1498143576000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6873681\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,7]]},"references-count":16,"URL":"https:\/\/doi.org\/10.1109\/iolts.2014.6873681","relation":{},"subject":[],"published":{"date-parts":[[2014,7]]}}}