{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,4]],"date-time":"2024-09-04T21:53:38Z","timestamp":1725486818143},"reference-count":20,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2015,7]]},"DOI":"10.1109\/iolts.2015.7229838","type":"proceedings-article","created":{"date-parts":[[2015,8,31]],"date-time":"2015-08-31T17:47:56Z","timestamp":1441043276000},"page":"89-94","source":"Crossref","is-referenced-by-count":3,"title":["Design space exploration and optimization of a Hybrid Fault-Tolerant Architecture"],"prefix":"10.1109","author":[{"given":"I.","family":"Wali","sequence":"first","affiliation":[]},{"given":"A.","family":"Virazel","sequence":"additional","affiliation":[]},{"given":"A.","family":"Bosio","sequence":"additional","affiliation":[]},{"given":"P.","family":"Girard","sequence":"additional","affiliation":[]},{"given":"M. Sonza","family":"Reorda","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"doi-asserted-by":"publisher","key":"ref10","DOI":"10.1109\/FTCS.1994.315626"},{"doi-asserted-by":"publisher","key":"ref11","DOI":"10.1109\/DSN.2002.1028924"},{"doi-asserted-by":"publisher","key":"ref12","DOI":"10.1145\/2024724.2024881"},{"doi-asserted-by":"publisher","key":"ref13","DOI":"10.1109\/ATS.2011.89"},{"doi-asserted-by":"publisher","key":"ref14","DOI":"10.1109\/VTS.2012.6231079"},{"year":"2006","author":"luciano","article-title":"EDA for IC Implementation, Circuit Design, and Process Technology","key":"ref15"},{"doi-asserted-by":"publisher","key":"ref16","DOI":"10.1145\/2593069.2593171"},{"doi-asserted-by":"publisher","key":"ref17","DOI":"10.1109\/PRDC.2008.54"},{"year":"0","key":"ref18"},{"doi-asserted-by":"publisher","key":"ref19","DOI":"10.1109\/TNS.2008.2006265"},{"doi-asserted-by":"publisher","key":"ref4","DOI":"10.1109\/DFT.2008.23"},{"doi-asserted-by":"publisher","key":"ref3","DOI":"10.1147\/rd.62.0200"},{"doi-asserted-by":"publisher","key":"ref6","DOI":"10.1109\/TVLSI.2006.887832"},{"doi-asserted-by":"publisher","key":"ref5","DOI":"10.1049\/iet-cdt.2008.0127"},{"doi-asserted-by":"publisher","key":"ref8","DOI":"10.1109\/JSSC.2008.2007145"},{"doi-asserted-by":"publisher","key":"ref7","DOI":"10.1109\/MICRO.2003.1253179"},{"year":"2007","author":"koren","article-title":"Fault Tolerant Systems","key":"ref2"},{"year":"2013","journal-title":"Semiconductor Industry Association","article-title":"International Technology Roadmap for Semiconductors (ITRS)","key":"ref1"},{"doi-asserted-by":"publisher","key":"ref9","DOI":"10.1109\/IOLTS.2011.5993832"},{"doi-asserted-by":"publisher","key":"ref20","DOI":"10.1109\/DDECS.2014.6868794"}],"event":{"name":"2015 IEEE 21st International On-Line Testing Symposium (IOLTS)","start":{"date-parts":[[2015,7,6]]},"location":"Halkidiki, Greece","end":{"date-parts":[[2015,7,8]]}},"container-title":["2015 IEEE 21st International On-Line Testing Symposium (IOLTS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7217973\/7229816\/07229838.pdf?arnumber=7229838","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,24]],"date-time":"2017-03-24T23:17:20Z","timestamp":1490397440000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7229838\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,7]]},"references-count":20,"URL":"https:\/\/doi.org\/10.1109\/iolts.2015.7229838","relation":{},"subject":[],"published":{"date-parts":[[2015,7]]}}}