{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,30]],"date-time":"2024-10-30T06:22:12Z","timestamp":1730269332773,"version":"3.28.0"},"reference-count":22,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2015,7]]},"DOI":"10.1109\/iolts.2015.7229847","type":"proceedings-article","created":{"date-parts":[[2015,8,31]],"date-time":"2015-08-31T21:47:56Z","timestamp":1441057676000},"page":"138-143","source":"Crossref","is-referenced-by-count":1,"title":["A single chip dependable and adaptable payload Data Processing Unit"],"prefix":"10.1109","author":[{"given":"Nektarios","family":"Kranitis","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Antonis","family":"Tsigkanos","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"George","family":"Theodorou","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ioannis","family":"Sideris","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Antonis","family":"Paschalis","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1016\/j.pss.2007.01.004"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4614-4903-4_12"},{"key":"ref12","article-title":"Correcting single-event upsets in Virtex-4 FPGA configuration Memory","author":"carmichael","year":"2009","journal-title":"XAPPI088 (v1 0)"},{"journal-title":"DS192 (v1 3)","article-title":"Radiation-Hardened, Space-Grade Virtex-5QV Family Overview","year":"2012","key":"ref13"},{"key":"ref14","article-title":"Compendium of XRTC Radiation Results on All Single-Event Effects Observed in the Virtex-5QV","author":"swift","year":"2011","journal-title":"Proc of the ReSpace\/MAPLD 2011 Conference"},{"article-title":"Recommendation for Managing the Configuration of the RHBD Virtex-5QV","year":"2011","author":"wang","key":"ref15"},{"key":"ref16","first-page":"475","article-title":"Enhanced Dynamic Reconfigurable Processing Module for Future Space Applications","author":"bubenhagen","year":"2010","journal-title":"Proceedings of the 3rd International Space Wire Conference (ISC)"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/AHS.2012.6268642"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/AHS.2012.6268666"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/AHS.2013.6604227"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2012.2231881"},{"key":"ref3","article-title":"SEU Strategies for Virtex-5 Devices","author":"chapman","year":"2010","journal-title":"XAPP864 (v2 0)"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/RME.2005.1543031"},{"journal-title":"ECSS-Q-HB-60–02 ESA-ESTEC","article-title":"Space engineering, product assurance. Techniques for Radiation Effects. Mitigation in ASICs and FPGAs","year":"0","key":"ref5"},{"key":"ref8","article-title":"FT-Unshades2: High Speed, High Capacity Fault Tolerance Emulation System","author":"aguirre","year":"2013","journal-title":"ESA Final Presentation Days ESTEC"},{"key":"ref7","article-title":"Predicting On-Orbit Static Single Event Upset Rates in Xilinx Virtex FPGAs","author":"engel","year":"2006","journal-title":"Los Alamos National Laboratory"},{"key":"ref2","article-title":"Triple Module Redundancy Design Techniques for Virtex FPGAs","volume":"v1 0 1","author":"carmichael","year":"2006","journal-title":"XAPP197"},{"key":"ref1","article-title":"ESAs Roadmap for Next Generation Payload Data Proscessors","author":"trautner","year":"2011","journal-title":"Proc of the 2011 Data Systems in Aerospace Conference (DASIA)"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/DFT.2007.45"},{"journal-title":"Gobham Gaisler Version 1 4 1","article-title":"GRLIB IP Core User's Manual","year":"2015","key":"ref20"},{"key":"ref22","article-title":"A Reconfigurable FPGA Implementation of CCSDS 121.0-B-2 Lossless Data Compression","author":"sideris","year":"2014","journal-title":"Proc On-board Payload Data Compression Workshop"},{"key":"ref21","article-title":"A Reconfigurable FPGA Implementation of CCSDS 122.0-B-l Image Data Compression for ESA PROBA-3 Coronagraph System Payload","author":"kranitis","year":"2014","journal-title":"Proc On-board Payload Data Compression Workshop"}],"event":{"name":"2015 IEEE 21st International On-Line Testing Symposium (IOLTS)","start":{"date-parts":[[2015,7,6]]},"location":"Halkidiki, Greece","end":{"date-parts":[[2015,7,8]]}},"container-title":["2015 IEEE 21st International On-Line Testing Symposium (IOLTS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7217973\/7229816\/07229847.pdf?arnumber=7229847","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,25]],"date-time":"2017-03-25T03:12:13Z","timestamp":1490411533000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7229847\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,7]]},"references-count":22,"URL":"https:\/\/doi.org\/10.1109\/iolts.2015.7229847","relation":{},"subject":[],"published":{"date-parts":[[2015,7]]}}}