{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,8,6]],"date-time":"2024-08-06T11:21:33Z","timestamp":1722943293435},"reference-count":23,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2018,7]]},"DOI":"10.1109\/iolts.2018.8474119","type":"proceedings-article","created":{"date-parts":[[2018,10,23]],"date-time":"2018-10-23T00:31:36Z","timestamp":1540254696000},"source":"Crossref","is-referenced-by-count":8,"title":["HealthLog Monitor: A Flexible System-Monitoring Linux Service"],"prefix":"10.1109","author":[{"given":"Athanasios","family":"Chatzidimitriou","sequence":"first","affiliation":[]},{"given":"George","family":"Papadimitriou","sequence":"additional","affiliation":[]},{"given":"Dimitris","family":"Gizopoulos","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","article-title":"Optimization of process parameter variation in 45nm p-channel MOSFET using L18 Orthogonal Array","author":"salehuddin","year":"2012","journal-title":"Semiconductor Electronics (ICSE) 201 IEEE International Conference on"},{"key":"ref11","article-title":"Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation","author":"ernst","year":"2003","journal-title":"IEEE\/ACM International Symposium on Microarchitecture (MICRO)"},{"key":"ref12","article-title":"Voltage emergency prediction: Using signatures to reduce operating margins","author":"reddi","year":"2009","journal-title":"International Conference on High-Performance Computer Architecture (HPCA)"},{"key":"ref13","article-title":"On Characterizing Near-Threshold SRAM Failures in FinFET Technology","author":"ganapathy","year":"2017","journal-title":"Proc the Annual Conference on Design Automation (DAC)"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/1394608.1382139"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/3123939.3124537"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2003.1225959"},{"key":"ref17","article-title":"A resilience roadmap","author":"nassif","year":"2010","journal-title":"DATE"},{"key":"ref18","article-title":"Using Register Lifetime Predictions to Protect Register Files Against Soft Errors","author":"montesinos","year":"2007","journal-title":"DSN"},{"key":"ref19","article-title":"A Low Energy Soft Error-Tolerant Register File Architecture for Embedded Processors","author":"fazeli","year":"2008","journal-title":"HASE"},{"key":"ref4","article-title":"Mcelog: memory error handling in user space","author":"kleen","year":"2018","journal-title":"Available http \/\/www halobates de\/lk10-mcelog pdf - Retrieved"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/LCA.2017.2766221"},{"key":"ref6","article-title":"ACPI Platform","year":"2018"},{"key":"ref5","article-title":"Linaro Kernel","year":"2018"},{"key":"ref8","article-title":"Intel 64 and IA-32 Architectures Software Developers Manual. Combined Volumes: 1, 2A, 2B, 2C, 3A, 3B and 3C","year":"2014"},{"key":"ref7","article-title":"Linux EDAC Documentation","year":"2018"},{"key":"ref2","article-title":"Using ECC Feedback to Guide Voltage Speculation in Low-Voltage Processors","author":"bacha","year":"2014","journal-title":"Proceedings of the IEEE\/ACM International Symposium on Microarchitecture (MICRO)"},{"key":"ref1","doi-asserted-by":"crossref","DOI":"10.1145\/2508148.2485948","article-title":"Dynamic reduction of voltage margins by leveraging on-chip ECC in Itanium II processors","author":"bacha","year":"2013","journal-title":"Proceedings of the International Symposium on Computer Architecture (ISCA)"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2005.69"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/2830772.2830824"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/CGO.2005.34"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/24.994913"},{"key":"ref23","article-title":"Multi-bit Error Tolerant Caches Using Two-Dimensional Error Coding","author":"kim","year":"2007","journal-title":"40tth Intternattiionall Symposiium on Miicroarchiittectture (MICRO)"}],"event":{"name":"2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS)","location":"Platja d'Aro","start":{"date-parts":[[2018,7,2]]},"end":{"date-parts":[[2018,7,4]]}},"container-title":["2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8450543\/8474071\/08474119.pdf?arnumber=8474119","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,8,24]],"date-time":"2020-08-24T03:29:10Z","timestamp":1598239750000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8474119\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,7]]},"references-count":23,"URL":"https:\/\/doi.org\/10.1109\/iolts.2018.8474119","relation":{},"subject":[],"published":{"date-parts":[[2018,7]]}}}