{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,30]],"date-time":"2024-10-30T06:22:56Z","timestamp":1730269376890,"version":"3.28.0"},"reference-count":23,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2018,7]]},"DOI":"10.1109\/iolts.2018.8474189","type":"proceedings-article","created":{"date-parts":[[2018,10,22]],"date-time":"2018-10-22T20:31:36Z","timestamp":1540240296000},"page":"275-280","source":"Crossref","is-referenced-by-count":8,"title":["Benchmarking the Capabilities and Limitations of SAT Solvers in Defeating Obfuscation Schemes"],"prefix":"10.1109","author":[{"given":"Shervin","family":"Roshanisefat","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Harshith K.","family":"Thirumala","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kris","family":"Gaj","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Houman","family":"Homayoun","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Avesta","family":"Sasan","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2017.7858346"},{"journal-title":"Proceedings of SAT Competition 2017 Solver and Benchmark Descriptions","year":"2017","author":"balyo","key":"ref11"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2010.284"},{"key":"ref13","doi-asserted-by":"crossref","DOI":"10.1145\/3194554.3194596","article-title":"SRCLock: SATResistant Cyclic Logic Locking for Protecting the Hardware","author":"roshanisefat","year":"2018","journal-title":"Proc of the on Great Lakes Symp on VLSI 2018"},{"key":"ref14","first-page":"1","article-title":"LUT-Lock: A Novel LUT-based Logic Obfuscation for FPGA-Bitstream and ASIC-Hardware Protection","author":"mardani","year":"2018","journal-title":"2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)"},{"key":"ref15","article-title":"Provably Secure Camouflaging Strategy for IC Protection","author":"li","year":"2017","journal-title":"IEEE Trans on Computer-Aided Design of Integrated Circuits and Systems"},{"key":"ref16","first-page":"502","article-title":"An Extensible SAT-solver","author":"een","year":"2003","journal-title":"Int'l Conf on Theory and Applications of Satisfiability Testing"},{"key":"ref17","article-title":"Glucose and Syrup in the SAT Race 2015","author":"audemard","year":"2015","journal-title":"SAT Race"},{"key":"ref18","article-title":"Lingeling, Plingeling and Treengeling Entering the SAT Competition 2013","volume":"2013","author":"biere","year":"2013","journal-title":"Proc SAT Competition"},{"key":"ref19","first-page":"123","article-title":"Learning Rate Based Branching Heuristic for SAT Solvers","author":"liang","year":"2016","journal-title":"Theory and applications of satisfiability testing Springer"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2015.2437996"},{"key":"ref3","first-page":"1","article-title":"Circuit Camouflage Integration for Hardware IP Protection","author":"cocchi","year":"2014","journal-title":"51st Design Automation Conference (DAC) 2014"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/HST.2015.7140252"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2016.7479225"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/HST.2016.7495588"},{"key":"ref7","article-title":"Integrated Circuit (IC) Decamouflaging: Reverse Engineering Camouflaged ICs within Minutes","author":"el","year":"2015","journal-title":"NDSS"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/MTV.2013.28"},{"volume":"2013","article-title":"Trends in the Global IC Design Service Market","year":"2013","key":"ref1"},{"key":"ref9","first-page":"127","article-title":"Mitigating SAT Attack on Logic Locking","author":"xie","year":"2016","journal-title":"Cryptographic Hardware & Embedded Systems Springer"},{"key":"ref20","article-title":"CryptoMiniSat","author":"soos","year":"2010","journal-title":"Solver Description SAT Race"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2013.193"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228377"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/IOLTS.2014.6873671"}],"event":{"name":"2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS)","start":{"date-parts":[[2018,7,2]]},"location":"Platja d'Aro","end":{"date-parts":[[2018,7,4]]}},"container-title":["2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8450543\/8474071\/08474189.pdf?arnumber=8474189","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,8,23]],"date-time":"2020-08-23T20:37:11Z","timestamp":1598215031000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8474189\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,7]]},"references-count":23,"URL":"https:\/\/doi.org\/10.1109\/iolts.2018.8474189","relation":{},"subject":[],"published":{"date-parts":[[2018,7]]}}}