{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,5]],"date-time":"2024-09-05T19:19:14Z","timestamp":1725563954740},"reference-count":19,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2018,7]]},"DOI":"10.1109\/iolts.2018.8474272","type":"proceedings-article","created":{"date-parts":[[2018,10,23]],"date-time":"2018-10-23T00:31:36Z","timestamp":1540254696000},"page":"265-268","source":"Crossref","is-referenced-by-count":1,"title":["Reliability And Performance Challenges Of Ultra-Low Voltage Caches: A Trade-Off Analysis"],"prefix":"10.1109","author":[{"given":"Anteneh","family":"Gebregiorgis","sequence":"first","affiliation":[]},{"given":"Mehdi B.","family":"Tahoori","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","article-title":"On transistor level gate sizing for increased robustness to transient faults","author":"cazeaux","year":"2005","journal-title":"IOLTS"},{"key":"ref11","article-title":"An analytical model for soft error critical charge of nanometric srams","author":"jahinuzzaman","year":"2009","journal-title":"TVLSI"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2011.2121913"},{"key":"ref13","article-title":"Impact of cmos technology scaling on the atmospheric neutron soft error rate","author":"hazucha","year":"2000","journal-title":"TNS"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.5772\/50111"},{"key":"ref15","doi-asserted-by":"crossref","DOI":"10.1145\/1816038.1816023","article-title":"Using hardware vulnerability factors to enhance avf analysis","author":"sridharan","year":"2010","journal-title":"Computer Architecture News"},{"key":"ref16","article-title":"An 8t-sram for variability tolerance and low-voltage operation in high-performance caches","author":"chang","year":"2008","journal-title":"JSSC"},{"key":"ref17","article-title":"A 256-kb 65-nm sub-threshold sram design for ultra-low-voltage operation","author":"calhoun","year":"2007","journal-title":"JSSC"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1016\/j.microrel.2009.03.016"},{"key":"ref19","doi-asserted-by":"crossref","DOI":"10.1145\/2024716.2024718","article-title":"The gem5 simulator","author":"binkert","year":"2011","journal-title":"Computer Architecture"},{"key":"ref4","article-title":"A process-tolerant cache architecture for improved yield in nanoscale technologies","author":"agarwal","year":"2005","journal-title":"TVLSI"},{"key":"ref3","article-title":"Trading off cache capacity for reliability to enable low voltage operation","author":"wilkerson","year":"2008","journal-title":"ISCA"},{"key":"ref6","article-title":"A low area overhead nbti\/pbti sensor for sram memories","author":"karimi","year":"2017","journal-title":"TVLSI"},{"key":"ref5","article-title":"Aging mitigation in memory arrays using self-controlled bitflipping technique","author":"gebregiorgis","year":"2015","journal-title":"ASP-DAC"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2013.2260357"},{"key":"ref7","article-title":"Soft error trends and mitigation techniques in memory devices","author":"slayman","year":"2011","journal-title":"RAMS"},{"key":"ref2","article-title":"Parichute: Generalized turbocode-based error correction for nearthreshold caches","author":"miller","year":"2010","journal-title":"Micro"},{"key":"ref1","article-title":"Ultra-low power vlsi circuit design demystified and explained: A tutorial","author":"alioto","year":"2012","journal-title":"TVLSI"},{"key":"ref9","article-title":"Analyzing the influence of voltage scaling for soft errors in sram-based fpgas","author":"tonfat","year":"2013","journal-title":"RADECS"}],"event":{"name":"2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS)","start":{"date-parts":[[2018,7,2]]},"location":"Platja d'Aro","end":{"date-parts":[[2018,7,4]]}},"container-title":["2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8450543\/8474071\/08474272.pdf?arnumber=8474272","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,8,24]],"date-time":"2020-08-24T06:18:05Z","timestamp":1598249885000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8474272\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,7]]},"references-count":19,"URL":"https:\/\/doi.org\/10.1109\/iolts.2018.8474272","relation":{},"subject":[],"published":{"date-parts":[[2018,7]]}}}