{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,22]],"date-time":"2026-01-22T01:02:58Z","timestamp":1769043778733,"version":"3.49.0"},"reference-count":22,"publisher":"IEEE","license":[{"start":{"date-parts":[[2019,7,1]],"date-time":"2019-07-01T00:00:00Z","timestamp":1561939200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2019,7,1]],"date-time":"2019-07-01T00:00:00Z","timestamp":1561939200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,7,1]],"date-time":"2019-07-01T00:00:00Z","timestamp":1561939200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2019,7]]},"DOI":"10.1109\/iolts.2019.8854379","type":"proceedings-article","created":{"date-parts":[[2019,10,4]],"date-time":"2019-10-04T00:27:48Z","timestamp":1570148868000},"page":"212-215","source":"Crossref","is-referenced-by-count":5,"title":["Characterization and Modeling of SET Generation Effects in CMOS Standard Logic Cells"],"prefix":"10.1109","author":[{"given":"Marko","family":"Andjelkovic","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yuanqing","family":"Li","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Zoran","family":"Stamenkovic","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Milos","family":"Krstic","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Rolf","family":"Kraemer","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2008.2003511"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2005.35"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/1391469.1391702"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1049\/iet-cds:20050210"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ISCID.2015.59"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/IRPS.2016.7574641"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.1982.4336490"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2009.2033798"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/IOLTS.2016.7604695"},{"key":"ref19","article-title":"A Critical Charge Model for Evaluation of SET and SEU Robustness &#x2013; A Muller C-Element Case Study","author":"andjelkovic","year":"2017","journal-title":"Proc ATS"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/2897937.2897976"},{"key":"ref3","article-title":"SEATLA: A Soft Error Analysis Tool for Combinational Logic","author":"rajaraman","year":"2006","journal-title":"Proc VLSID"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1016\/j.mejo.2016.01.007"},{"key":"ref5","first-page":"217","article-title":"A Detailed Methodology to Compute Soft Error Rates in Advanced Technologies","author":"marc riera","year":"2016","journal-title":"Design Automation Test in Europe Conference Exhibition (DATE)"},{"key":"ref8","article-title":"Design Optimization for Single Event Upset Robustness Using Simultaneous dual-Vdd and Sizing Techniques","author":"choudry","year":"2006","journal-title":"Proc ICCAD"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/23.819093"},{"key":"ref2","article-title":"Towards Formal Abstraction, Modeling and Analysis of Single Event Transients at RTL","author":"hamad","year":"2010","journal-title":"Proc ISCAS"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TDSC.2004.14"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2009.2020391"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/MIEL.2017.8190106"},{"key":"ref22","article-title":"SPICE-based SET Pulse Width Model","author":"andjelkovic","year":"2019","journal-title":"Proc GI\/GMM\/ITG TuZ"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/EWDTS.2018.8524748"}],"event":{"name":"2019 IEEE 25th International Symposium on On-Line Testing And Robust System Design (IOLTS)","location":"Rhodes, Greece","start":{"date-parts":[[2019,7,1]]},"end":{"date-parts":[[2019,7,3]]}},"container-title":["2019 IEEE 25th International Symposium on On-Line Testing and Robust System Design (IOLTS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8846168\/8854369\/08854379.pdf?arnumber=8854379","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,17]],"date-time":"2022-07-17T21:50:51Z","timestamp":1658094651000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8854379\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,7]]},"references-count":22,"URL":"https:\/\/doi.org\/10.1109\/iolts.2019.8854379","relation":{},"subject":[],"published":{"date-parts":[[2019,7]]}}}