{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,30]],"date-time":"2024-10-30T06:23:57Z","timestamp":1730269437623,"version":"3.28.0"},"reference-count":16,"publisher":"IEEE","license":[{"start":{"date-parts":[[2022,9,12]],"date-time":"2022-09-12T00:00:00Z","timestamp":1662940800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2022,9,12]],"date-time":"2022-09-12T00:00:00Z","timestamp":1662940800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2022,9,12]]},"DOI":"10.1109\/iolts56730.2022.9897297","type":"proceedings-article","created":{"date-parts":[[2022,9,27]],"date-time":"2022-09-27T19:57:10Z","timestamp":1664308630000},"page":"1-6","source":"Crossref","is-referenced-by-count":1,"title":["Recovering Information on the CVA6 RISC-V CPU with a Baremetal Micro-Architectural Covert Channel"],"prefix":"10.1109","author":[{"given":"Valentin","family":"Martinoli","sequence":"first","affiliation":[{"name":"Cybersecurity Hardware lab, Thales DIS,La Ciotat,France"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yannick","family":"Teglia","sequence":"additional","affiliation":[{"name":"Cybersecurity Hardware lab, Thales DIS,La Ciotat,France"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Bouagoun","family":"Abdellah","sequence":"additional","affiliation":[{"name":"Cybersecurity Hardware lab, Thales DIS,La Ciotat,France"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Regis","family":"Leveugle","sequence":"additional","affiliation":[{"name":"Univ. Grenoble Alpes,CNRS, Grenoble INP Institute of Engineering Univ. Grenoble Alpes, TIMA,Grenoble,France,38000"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"journal-title":"ETH Zurich","article-title":"CVA6 Core","year":"2022","key":"ref10"},{"key":"ref11","article-title":"CVA6's Data cache: Structure and Behavior","author":"martinoli","year":"2022","journal-title":"arXiv e-prints 2202 03749"},{"journal-title":"Veripool","article-title":"Verilator","year":"2022","key":"ref12"},{"journal-title":"RISC-V","article-title":"Spike RIDC-V ISA Simulator","year":"2022","key":"ref13"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/3173162.3173204"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/3372297.3417268"},{"key":"ref16","article-title":"Advanced Encryption Standard (AES)","author":"dworkin","year":"2001","journal-title":"Federal Inf Process Stds (NIST FIPS) National Institute of Standards and Technology"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/SP.2019.00087"},{"key":"ref3","article-title":"Fallout: Reading Kernel Writes From User Space","author":"canella","year":"2019","journal-title":"26th ACM Conf on Computer and Commubications Security"},{"key":"ref6","first-page":"203","article-title":"A Comparison Study on Flush + Reload and Prime + Probe Attacks on AES Using Machine Learning Approaches","author":"allaf","year":"2017","journal-title":"UK Workshop on Computational Intelligence"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/3319535.3354252"},{"key":"ref8","doi-asserted-by":"crossref","first-page":"279","DOI":"10.1007\/978-3-319-40667-1_14","article-title":"Flush + Flush: A Fast and Stealthy Cache Attack","volume":"9721","author":"gruss","year":"2016","journal-title":"Detection of Intrusions and Malware and Vulnerability Assessment"},{"key":"ref7","first-page":"719","article-title":"FLUSH + RELOAD: a High Resolution, Low Noise, L3 Cache Side-Channel Attack","author":"yuval","year":"2014","journal-title":"23rd USENIX Security Symposium (USENIX Security 14)"},{"key":"ref2","article-title":"Foreshadow: Extracting the Keys to the Intel SGX Kingdom with Transient Out-of-Order Execution","author":"bulck","year":"2018","journal-title":"27th USENIX Security Symposium ( USENIX Security 18) USENIX Association"},{"journal-title":"JSOF","article-title":"Ripple20: 19 Zero-Day Vulnerabilities Amplified by the Supply Chain","year":"2020","key":"ref1"},{"key":"ref9","first-page":"51","article-title":"Prime + Abort: A Timer-Free High-Precision L3 Cache Attack using Intel TSX","author":"disselkoen","year":"2017","journal-title":"26th USENIX Security Symposium (USENIX Security 17)"}],"event":{"name":"2022 IEEE 28th International Symposium on On-Line Testing and Robust System Design (IOLTS)","start":{"date-parts":[[2022,9,12]]},"location":"Torino, Italy","end":{"date-parts":[[2022,9,14]]}},"container-title":["2022 IEEE 28th International Symposium on On-Line Testing and Robust System Design (IOLTS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9897157\/9897171\/09897297.pdf?arnumber=9897297","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,10,14]],"date-time":"2022-10-14T20:54:35Z","timestamp":1665780875000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9897297\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,9,12]]},"references-count":16,"URL":"https:\/\/doi.org\/10.1109\/iolts56730.2022.9897297","relation":{},"subject":[],"published":{"date-parts":[[2022,9,12]]}}}